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![[root]](/resources/fpga/xilinx/interposer/common_sdp?ns=&tab_files=files&do=media&tab_details=history&image=resources%3Afpga%3Adocs%3Aaxi_logic_analyzer_diagram.png){kind=link}
![resources:fpga:docs:axi_logic_analyzer_diagram.png [10 Jun 2019 21:30]](/_detail/resources/fpga/docs/axi_logic_analyzer_diagram.png?rev=1560195001){kind=link}
![resources:fpga:docs:axi_logic_analyzer_diagram.png [04 Sep 2020 12:23]](/_detail/resources/fpga/docs/axi_logic_analyzer_diagram.png){kind=link}