This document presents the steps to setup an environment for using the EVAL-CN0189-SDPZ evaluation board together with the Xilinx KC705 FPGA board and the Xilinx Embedded Development Kit (EDK). Below is presented a picture of the EVAL-CN0189-SDPZ Evaluation Board with the Xilinx KC705 board.
For component evaluation and performance purposes, as opposed to quick prototyping, the user is directed to use the part evaluation setup. This consists of:
The SDP-B controller board is part of Analog Devices System Demonstration Platform (SDP). It provides a high speed USB 2.0 connection from the PC to the component evaluation board. The PC runs the evaluation software. Each evaluation board, which is an SDP compatible daughter board, includes the necessary installation file required for performance testing.
Note: it is expected that the analog performance on the two platforms may differ.
Below is presented a picture of SDP-B Controller Board with the EVAL-CN0189-SDPZ Evaluation Board.
The CN-0189 circuit incorporates a dual axis ADXL203 accelerometer and the AD7887 12-bit successive approximation (SAR) ADC to create a dual axis tilt measurement system. The ADXL203 is a polysilicon surface micromachined sensor and signal conditioning circuit. Acceleration in the X or Y axis will produce a corresponding output voltage on the XOUT or YOUT output pins of the device. The X axis and Y axis are perpendicular to one another. The AD8608 quad op amp buffers, attenuates, and level shifts the [adi>ADXL203]] outputs so they are at the proper levels to drive the inputs of the AD7887. The rail-to-rail input/output AD8608 is chosen for its low offset voltage (65 μV maximum), low bias current (1 pA maximum), low noise (8 nV/√Hz), and small footprint (14-lead SOIC or TSSOP). The AD7887 is configurable for either dual or single channel operation via the on-chip control register. In this application it is configured for dual channel mode, allowing the user to monitor both outputs of the ADXL203, thereby providing a more accurate and complete solution.
The first objective is to ensure that you have all of the items needed and to install the software tools so that you are ready to create and run the evaluation project.
Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage of the KC705 is set to 3.3V. For more details on how to change the setting for VADJ_FPGA visit the Xilinx KC705 product page.
The following commands were implemented in this version of EVAL-CN0189 reference project for Xilinx KC705 FPGA board.
|help?||Displays all available commands.|
|calibX+1G!||Acquire data for calibration, when Xacc=+1[g].|
|calibX-1G!||Acquire data for calibration, when Xacc=-1[g].|
|calibY+1G!||Acquire data for calibration, when Yacc=+1[g].|
|calibY-1G!||Acquire data for calibration, when Yacc=-1[g].|
|calibCalculateParam!||Calculates the parameters for calibration.|
|rawData?||Displays the raw data an both axes.(40 samples)|
|acceleration?||Displays the acceleration on both axes.(40 samples)|
|tilt?||Displays the tilt on both axes.(40 samples)|
Commands can be executed using a serial terminal connected to the UART peripheral of Xilinx KC705 FPGA.
The following image shows a generic list of commands in a serial terminal connected to Xilinx KC705 FPGA's UART peripheral.
The hardware platform for each reference projects with FMC-SDP interposer and KC705 evaluation board is common. The next steps should be followed to recreate the software project of the reference design: