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- board_pic.png
- 986×388
- 10 Jan 2023 05:33
- 481.7 KB
- fixed_max31855_max32650.png
- 658×542
- 27 Mar 2023 10:15
- 308.4 KB
- fixed_max31855_max32655.png
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- 27 Mar 2023 10:15
- 93.5 KB
- layout.png
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- 10 Jan 2023 06:20
- 38.5 KB
- max31855pmb1.zip
- 11 Jan 2023 03:01
- 281.6 KB
- max31855_debug_panel.png
- 862×832
- 27 Mar 2023 08:57
- 131.4 KB
- max31855_dmm_panel.png
- 619×597
- 27 Mar 2023 05:52
- 48.4 KB
- max31855_max32650.png
- 654×594
- 11 Jan 2023 03:01
- 308.4 KB
- max31855_max32650_basic_example.png
- 665×405
- 30 Mar 2023 05:50
- 11.9 KB
- max31855_max32650_demo.jpg
- 2048×1151
- 11 Jan 2023 02:04
- 97.6 KB
- max31855_max32650_iio_debug_panel.png
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- 30 Mar 2023 05:50
- 22.2 KB
- max31855_max32650_iio_dmm_panel.png
- 648×528
- 30 Mar 2023 05:50
- 18 KB
- max31855_max32650_iio_example.png
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- 30 Mar 2023 05:50
- 15 KB
- max31855_max32650_iio_osc.png
- 420×590
- 30 Mar 2023 05:50
- 21.9 KB
- max31855_max32655.png
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- 11 Jan 2023 02:04
- 93.5 KB
- max31855_max32655_basic_example.png
- 665×502
- 30 Mar 2023 05:50
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- max31855_max32655_demo.jpg
- 2048×1151
- 11 Jan 2023 02:07
- 91 KB
- max31855_max32655_demo.png
- 1767×1139
- 11 Jan 2023 02:22
- 823.8 KB
- max31855_max32655_iio_debug_panel.png
- 639×517
- 30 Mar 2023 05:50
- 20.3 KB
- max31855_max32655_iio_dmm_panel.png
- 636×516
- 30 Mar 2023 05:50
- 16.8 KB
- max31855_max32655_iio_example.png
- 668×425
- 30 Mar 2023 05:50
- 15.5 KB
- max31855_max32655_iio_osc.png
- 410×581
- 30 Mar 2023 05:50
- 21.2 KB
- max31855_osc.png
- 593×707
- 27 Mar 2023 05:55
- 123 KB
- max32650fthr_with_pico.png
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- 27 Mar 2023 10:37
- 453.7 KB
- spi_port.png
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- 10 Jan 2023 05:43
- 36 KB
resources/fpga/xilinx/interposer/cn0188.txt · Last modified: 09 Jan 2021 00:49 by Robin Getz