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| resources:fpga:xilinx:interposer:cn0187 [18 Nov 2013 15:28] – changed source code (without Micrium uC-Probe), added Software Setup, remove programming with Impact Lucian Sin | resources:fpga:xilinx:interposer:cn0187 [29 Dec 2020 20:27] – fix link Robin Getz | ||
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| The **EVAL-CN0187-SDPZ** measures peak and rms power at any RF frequency from 450 MHz to 6 GHz over a range of approximately 45 dB. The measurement results are converted to differential signals in order to eliminate noise and are provided as digital codes at the output of a 12-bit SAR ADC with serial interface and integrated reference. When using this evaluation board with the SDP board or BeMicro SDK board, apply +6 V and GND to Power Connector. | The **EVAL-CN0187-SDPZ** measures peak and rms power at any RF frequency from 450 MHz to 6 GHz over a range of approximately 45 dB. The measurement results are converted to differential signals in order to eliminate noise and are provided as digital codes at the output of a 12-bit SAR ADC with serial interface and integrated reference. When using this evaluation board with the SDP board or BeMicro SDK board, apply +6 V and GND to Power Connector. | ||
| - | The [[adi>AD72661]] is a dual, 12-bit, high speed, low power, successive approximation ADC that operates from a single 2.7 V to 5.25 V power supply and features throughput rates up to 2 MSPS. The device contains two ADCs, each preceded by a 3-channel multiplexer, | + | The [[adi>AD7266]] is a dual, 12-bit, high speed, low power, successive approximation ADC that operates from a single 2.7 V to 5.25 V power supply and features throughput rates up to 2 MSPS. The device contains two ADCs, each preceded by a 3-channel multiplexer, |
| The conversion process and data acquisition use standard control inputs allowing easy interfacing to microprocessors or DSPs. The input signal is sampled on the falling edge of CS; conversion is also initiated at this point. The conversion time is determined by the SCLK frequency. There are no pipelined delays associated with the part. | The conversion process and data acquisition use standard control inputs allowing easy interfacing to microprocessors or DSPs. The input signal is sampled on the falling edge of CS; conversion is also initiated at this point. The conversion time is determined by the SCLK frequency. There are no pipelined delays associated with the part. | ||
resources/fpga/xilinx/interposer/cn0187.txt · Last modified: 09 Jan 2021 00:49 by Robin Getz