Wiki

Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revisionPrevious revision
Next revision
Previous revision
resources:fpga:xilinx:interposer:admp441 [16 Nov 2012 16:28] – [Evaluation Boards] fixup eval board link Lars-Peter Clausenresources:fpga:xilinx:interposer:admp441 [14 Jan 2021 06:09] (current) – use xilinx> interwiki links Robin Getz
Line 30: Line 30:
   * [[adi>ADMP441|ADMP441 Product Info]] - pricing, samples, datasheet   * [[adi>ADMP441|ADMP441 Product Info]] - pricing, samples, datasheet
   * {{http://www.analog.com/static/imported-files/user_guides/UG-303.pdf|EVAL-ADMP441Z evaluation board user guide}}   * {{http://www.analog.com/static/imported-files/user_guides/UG-303.pdf|EVAL-ADMP441Z evaluation board user guide}}
-  * [[http://www.xilinx.com/products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]+  * [[xilinx>products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]
  
 ====== Getting Started ====== ====== Getting Started ======
Line 38: Line 38:
 ===== Required Hardware ===== ===== Required Hardware =====
  
-  * [[http://www.xilinx.com/products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]+  * [[xilinx>products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]
   * FMC-SDP adapter board   * FMC-SDP adapter board
   * **EVAL-ADMP441Z** evaluation board   * **EVAL-ADMP441Z** evaluation board
Line 63: Line 63:
 ===== Hardware Setup ===== ===== Hardware Setup =====
  
-<note important>Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage of the KC705 is set to 3.3V. For more details on how to change the setting for VADJ_FPGA visit the Xilinx KC705 product page.</note>+<WRAP important>Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage of the KC705 is set to 3.3V. For more details on how to change the setting for VADJ_FPGA visit the Xilinx KC705 product page.</WRAP>
  
   * Use the FMC-SDP interposer to connect the ADI evaluation board to the Xilinx KC705 board on the FMC LPC connector.   * Use the FMC-SDP interposer to connect the ADI evaluation board to the Xilinx KC705 board on the FMC LPC connector.
Line 75: Line 75:
 At this point everything is set up and it is possible to start the evaluation of the ADI hardware. To capture data from the microphones run the //data_capture.bat// script located in the //DataCapture// folder from the reference design .zip file. Every time the script is run, 20 seconds of audio data is recorded at 25000 Hz sample rate, and saved in **EVAL_ADMP441Z_Demo.wav**. The user can change the sample rate by modifying the value stored in Timer0, and the duration of the recording in seconds, by modifying the nrSeconds variable in **main.c**. The sample rate is calculated according to the period of the WS signal. If the user chooses to modify the duration of the recording, modifications must also be made in the tcl script in order to acquire the desired number of samples (for 20 seconds of audio data, the script acquires data for 10 * 100000 times). At this point everything is set up and it is possible to start the evaluation of the ADI hardware. To capture data from the microphones run the //data_capture.bat// script located in the //DataCapture// folder from the reference design .zip file. Every time the script is run, 20 seconds of audio data is recorded at 25000 Hz sample rate, and saved in **EVAL_ADMP441Z_Demo.wav**. The user can change the sample rate by modifying the value stored in Timer0, and the duration of the recording in seconds, by modifying the nrSeconds variable in **main.c**. The sample rate is calculated according to the period of the WS signal. If the user chooses to modify the duration of the recording, modifications must also be made in the tcl script in order to acquire the desired number of samples (for 20 seconds of audio data, the script acquires data for 10 * 100000 times).
  
-<note tip>The first time the data capture script is run it is possible that an error will occur while the script is trying to connect to the system. Just run the script again and the error shouldn't appear anymore. The same applies if you do not see any waveforms on the WS or SCLK pins on the evaluation board. </note>+<WRAP tip>The first time the data capture script is run it is possible that an error will occur while the script is trying to connect to the system. Just run the script again and the error shouldn't appear anymore. The same applies if you do not see any waveforms on the WS or SCLK pins on the evaluation board. </WRAP>
  
 ====== More information ====== ====== More information ======
 {{page>ez_common}} {{page>ez_common}}
resources/fpga/xilinx/interposer/admp441.txt · Last modified: 14 Jan 2021 06:09 by Robin Getz