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resources:fpga:xilinx:interposer:adf4156 [28 May 2012 15:53] – Approved Alexandru.Tofan | resources:fpga:xilinx:interposer:adf4156 [04 Nov 2013 08:54] – changed source code (without Micrium uC-Probe), added Software Setup, remove programming with Impact Lucian Sin | ||
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====== Overview ====== | ====== Overview ====== | ||
- | This document presents the steps to setup an environment for using the **[[http:// | + | This document presents the steps to setup an environment for using the **[[http:// |
{{ : | {{ : | ||
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* [[adi>/ | * [[adi>/ | ||
* [[http:// | * [[http:// | ||
- | * [[http:// | ||
====== Getting Started ====== | ====== Getting Started ====== | ||
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===== Required Software ===== | ===== Required Software ===== | ||
- | * Xilinx ISE 13.4 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack). | + | * Xilinx ISE 14.6. |
- | * [[http://micrium.com/ | + | * UART Terminal (Termite/Tera Term/Hyperterminal), |
+ | * The EVAL-ADF4156 reference project for Xilinx KC705 FPGA. | ||
===== Downloads ===== | ===== Downloads ===== | ||
- | + | <WRAP round download 80%> | |
- | * {{:resources: | + | \\ |
- | + | * **ADF4156 Driver:** https://github.com/ | |
- | The following table presents a short description the reference design archive contents. | + | * **ADF4156 Commands:** https:// |
- | + | | |
- | ^ **Folder** ^ **Description** ^ | + | * **EDK KC705 Reference |
- | | Bit | Contains the KC705 configuration file that can be used to program the system for quick evaluation. | | + | \\ |
- | | Microblaze | Contains the EDK 13.4 project for the Microblaze softcore that will be implemented in the KC705 FPGA. | | + | </ |
- | | Software | Contains the source files of the software | + | |
- | | uCProbeInterface | Contains the uCProbe interface and the .elf symbols file used by uC-Probe to access data from the Microblaze memory. | | + | |
====== Run the Demonstration Project ====== | ====== Run the Demonstration Project ====== | ||
- | {{page> | + | ===== Hardware setup ===== |
- | + | ||
- | ===== Demonstration Project User Interface | + | |
- | + | ||
- | The following figure presents the **uC-Probe** interface that can be used for monitoring and controlling the operation of the **EVAL-ADF4156SD1Z** evaluation board. | + | |
- | + | ||
- | {{ : | + | |
- | + | ||
- | **Section A** allows turning the communication with the Evaluation Board ON or OFF by toggling the switch. The green LED on the switch will turn on when communication is active. Before pressing the //ON/OFF// switch, make sure you select the desired //Device Initialization Procedure// | + | |
- | + | ||
- | **Section B** allows controlling the output on MUXOUT. Set to 1 for DVdd, 2 for GND or 7 for SDO (can be used to test if communication with board is active). | + | |
- | + | ||
- | **Section C** allows setting Fractional, Integer, Phase, Current, R Counter and Modulus Values. See pg. 17 of datasheet for calculated examples of these values. | + | |
- | **Section D** allows setting or clearing certain control bits in Register R2 and R3. See datasheet pg. 13 for details. | + | <WRAP round important 80%> |
+ | \\ | ||
+ | Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage of the KC705 is set to 3.3V. For more details | ||
+ | </ | ||
- | **Section E** selects Clkock Divider Mode. | + | |
+ | | ||
- | **Section F** selects Clock Divider Value. | + | ===== Reference Project Overview ===== |
+ | The following commands were implemented in this version of EVAL-ADF4156 reference project for Xilinx KC705 FPGA board. | ||
+ | ^ Command ^ Description ^ | ||
+ | | **help?** | Displays all available commands. | | ||
+ | | **frequency=** | Sets the desired output frequency in MHz. Accepted values:\\ 500 ... 6200 - desired output frequency in MHz. | | ||
+ | | **frequency? | ||
+ | | **register=** | Sets the value of the desired register on 29 bits. Accepted values:\\ register:\\ 0 .. 4 - the selected register.\\ value:\\ 0 .. 0x1FFFFFFF - the new value of the register. | | ||
+ | | **register? | ||
+ | | **PFDfreq?** | Displays the current PFD frequency in MHz. | | ||
+ | |||
- | **Section G** is used to apply settings. After setting everything as desired, press this button to send data to the ADF4156. | + | Commands can be executed using a serial terminal connected |
- | ===== Troubleshooting ===== | + | The following image shows a generic list of commands in a serial terminal connected to Xilinx KC705 FPGA's UART peripheral. |
+ | {{ : | ||
- | In case there is a communication problem with the board the follwing actions can be perfomed in order to try to fix the issues: | + | ===== Software Project Setup ===== |
- | * Check that the evaluation board is powered as instructed in the board' | + | {{page> |
- | * In uC-Probe refresh the symbols file by right-clicking on the **//System Browser//** window and selecting **//Refresh Symbols// | + | |
- | * If the communication problem persists even after performing the previous steps, restart the uC-Probe application and try to run the interface again. | + | |
====== More information ====== | ====== More information ====== | ||
{{page> | {{page> |