Wiki

Analog Devices Wiki

English
English
简体中文
简体中文
日本語
日本語
Руccкий
Руccкий

Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Next revision		Previous revision
resources:fpga:xilinx:interposer:adf4106 [26 Jul 2012 13:19] – created Alexandru.Tofanresources:fpga:xilinx:interposer:adf4106 [09 Jan 2021 00:49] (current) – user interwiki links Robin Getz
Line 7: Line 7:
 ===== Evaluation Boards ===== ===== Evaluation Boards =====
  
-  * [[adi>EVAL-ADF4106SD1Z]] +  * [[adi>EVAL-ADF4106|EVAL-ADF4106SD1Z]]
 ====== Overview ====== ====== Overview ======
  
-This document presents the steps to setup an environment for using the **[[adi>ADF4106|EVAL-ADF4106SD1Z]]** evaluation board together with the Xilinx KC705 FPGA board, the Xilinx Embedded Development Kit (EDK) and the [[http://micrium.com/page/products/tools/probe|Micrium µC-Probe]] run-time monitoring tool. Below is presented a picture of the EVAL-ADF4106SD1Z Evaluation Board with the Xilinx KC705 board.+This document presents the steps to setup an environment for using the **[[adi>ADF4106|EVAL-ADF4106SD1Z]]** evaluation board together with the Xilinx KC705 FPGA board and the Xilinx Embedded Development Kit (EDK). Below is presented a picture of the EVAL-ADF4106SD1Z Evaluation Board with the Xilinx KC705 board.
  
-{{ :resources:fpga:xilinx:interposer:img_adf4106.jpg }}+{{ :resources:fpga:xilinx:interposer:img_adf4106.jpg?400 }}
  
 For component evaluation and performance purposes, as opposed to quick prototyping, the user is directed to Analog Devices [[/resources/eval/sdp|System Demonstration Platform]] (**SDP**). The **SDP** consists of a: For component evaluation and performance purposes, as opposed to quick prototyping, the user is directed to Analog Devices [[/resources/eval/sdp|System Demonstration Platform]] (**SDP**). The **SDP** consists of a:
Line 28: Line 27:
   * [[adi>ADF4106|ADF4106 Product Info]] - pricing, samples, datasheet   * [[adi>ADF4106|ADF4106 Product Info]] - pricing, samples, datasheet
   * [[adi>/static/imported-files/user_guides/UG-159.pdf|EVAL-ADF4106SD1Z evaluation board user guide]]   * [[adi>/static/imported-files/user_guides/UG-159.pdf|EVAL-ADF4106SD1Z evaluation board user guide]]
-  * [[http://www.xilinx.com/products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]] +  * [[xilinx>products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]
-  * [[http://micrium.com/page/products/tools/probe|Micrium uC-Probe]]+
  
 ====== Getting Started ====== ====== Getting Started ======
Line 37: Line 35:
 ===== Required Hardware ===== ===== Required Hardware =====
  
-  * [[http://www.xilinx.com/products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]+  * [[xilinx>products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]
   * FMC-SDP adapter board   * FMC-SDP adapter board
   * **EVAL-ADF4106SD1Z** evaluation board   * **EVAL-ADF4106SD1Z** evaluation board
Line 43: Line 41:
 ===== Required Software ===== ===== Required Software =====
  
-  * Xilinx ISE 13.4 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack). +  * Xilinx ISE 14.6 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack). 
-  * [[http://micrium.com/page/products/tools/probe|uC-Probe]] run-time monitoring tool+  * UART Terminal (Termite/Tera Term/Hyperterminal), baud rate 115200.
  
 ===== Downloads ===== ===== Downloads =====
  
-  * {{:resources:fpga:xilinx:interposer:adf4106_evalboard.zip|Reference Design Files}} +<WRAP round download 80%> 
- +\\ 
-The following table presents a short description the reference design archive contents. +  * **ADF4106 Driver:** https://github.com/analogdevicesinc/no-OS/tree/master/drivers/frequency/adf4106 
- +  * **ADF4106 Commands:** https://github.com/analogdevicesinc/no-OS/tree/master/device_commands/ADF4106 
-^ **Folder** ^ **Description** ^ +  * **Xilinx Boards Common Drivers:** https://github.com/analogdevicesinc/no-OS/tree/master/platform_drivers/Xilinx/SDP_Common 
-| Bit | Contains the KC705 configuration file that can be used to program the system for quick evaluation. | +  * **EDK KC705 Reference project:** https://github.com/analogdevicesinc/fpgahdl_xilinx/tree/master/cf_sdp_kc705 
-| Microblaze | Contains the EDK 13.4 project for the Microblaze softcore that will be implemented in the KC705 FPGA. | +\\ 
-| Software | Contains the source files of the software project that will be run by the Microblaze processor.| +</WRAP>
-| uCProbeInterface | Contains the uCProbe interface and the .elf symbols file used by uC-Probe to access data from the Microblaze memory. | +
- +
-====== Run the Demonstration Project ====== +
- +
-{{page>ucprobe_common}} +
- +
-===== Demonstration Project User Interface ===== +
- +
-The following figure presents the **uC-Probe** interface that can be used for monitoring and controlling the operation of the **EVAL-ADF4106SD1Z** evaluation board. +
- +
-{{ :resources:fpga:altera:bemicro:adf4106_interface.png?700 }}+
  
-**Section A** allows for the communication with the board to be activated / deactivated by toggling the //ON/OFF// switch. The //Activity// LED turns green when the communication is active. Before pressing the //ON/OFF// switch, make sure you select the desired //Device Initialization Procedure//. If the //ON/OFF// switch is set to ON and the //Activity// LED is BLACK it means that there is a communication problem with the board. See the **Troubleshooting** section for indications on how to fix the communication problems.+===== Hardware setup =====
  
-**Sections B, C and D** allow for configuration of each latch on the **ADF4106**.+<WRAP round important 80%> 
 +\\ 
 +Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage of the KC705 is set to 3.3V. For more details on how to change the setting for VADJ_FPGA visit the Xilinx KC705 product page. 
 +</WRAP>
  
-**Section B** allows for the configuration of the //Reference Counter Latch//. The //LDP// switch allows setting the number of consecutive cycles of phase delay that must occur before Lock Detect is Set (0 = 3 Cycles, 1 = 5 Cycles). //ABP2// and //ABP1// allow setting the AntiBackLash Pulse Width. The //Slider// allows setting the R Divider. Pressing the //Write R// button programs the R Counter latch.+  * Use the FMC-SDP interposer to connect the ADI evaluation board to the Xilinx KC705 board on the FMC LPC connector. 
 +  * Connect the JTAG and UART cables to the KC705 and power up the FPGA board.
  
-**Section C** allows for the configuration of the //N Counter Latch//. The //CP Gain// switch allows toggling between different settings for the charge pump. The //B Slider// allows setting the B Counter value, while the //A Slider// allows setting the value for the A Counter. The //Write N// button programs the N Counter Latch.+===== Reference Project Overview ===== 
 +The following commands were implemented in this version of EVAL-ADF4106SD1Z reference project for Xilinx KC705 FPGA board. 
 +^ Command ^ Description ^ 
 +| **help?** | Displays all available commands. | 
 +| **register=** | Update the selected latch with the current set ups. Accepted value:\\ latch:\\ 0 - Reference latch\\ 1 - N Counter Latch\\ 2 - Function Latch\\ 3 - Initialization Latch\\ value:\\ 24 bit values, you can find more information about the registers in the data sheet | 
 +| **register?** | Print the specified latch values in a human readable format. Accepted value:\\ latch:\\ 0 - Reference latch\\ 1 - N Counter Latch\\ 2 - Function Latch\\ 3 - Initialization Latch | 
 +| **frequency=** | Set the VCO frequency. Accepted value:\\ 5 .. 6000 - betwwen 5Mhz and 6Ghz | 
 +| **frequency?** | Print the actual VCO frequency. |
  
-**Sections D** allows programming both the //Initialization Latch// and the //Function Latch//. The //CE//, //PD2// and //PD1// switches are user to select the Power Down Mode. //Current Setting 2// and //Current Setting 1// sliders are used to set the value of Icp (mA). //Timer Control// sets the timeout in PFD CYCLES. //MUXOUT// slider is used to select different functions for the MUXOUT pin. Fastlock can be enabled by toggling the //Fastlock EN// switch, while the //Counter RST// switch is used to reset the counters. Pressing the //Write Func// button will program the Function Latch. Pressing the //Write INIT// button will program the Initialization Latch.+Commands can be executed using a serial terminal connected to the UART peripheral of Xilinx KC705 FPGA.
  
-===== Troubleshooting =====+The following image shows a generic list of commands in a serial terminal connected to Xilinx KC705 FPGA's UART peripheral. 
 +{{ :resources:fpga:xilinx:interposer:Terminal_KC705.jpg? }}
  
-In case there is a communication problem with the board the follwing actions can be perfomed in order to try to fix the issues: +===== Software Project Setup ===== 
-  * Check that the evaluation board is powered as instructed in the board's user guide. +{{page>import_workspace}}
-  * In uC-Probe refresh the symbols file by right-clicking on the **//System Browser//** window and selecting **//Refresh Symbols//**. +
-  * If the communication problem persists even after performing the previous steps, restart the uC-Probe application and try to run the interface again.+
  
 ====== More information ====== ====== More information ======
 {{page>ez_common}} {{page>ez_common}}
resources/fpga/xilinx/interposer/adf4106.txt · Last modified: 09 Jan 2021 00:49 by Robin Getz

Page Tools