This shows you the differences between two versions of the page.
Both sides previous revisionPrevious revisionNext revision | Previous revision | ||
resources:fpga:xilinx:interposer:adf4002 [30 Oct 2013 14:24] – Delete ucProbe references, added UART interface snapshots and descriptions Istvan Csomortani | resources:fpga:xilinx:interposer:adf4002 [09 Jan 2021 00:49] (current) – user interwiki links Robin Getz | ||
---|---|---|---|
Line 27: | Line 27: | ||
* [[adi> | * [[adi> | ||
* [[adi>/ | * [[adi>/ | ||
- | * [[http://www.xilinx.com/products/ | + | * [[xilinx>products/ |
====== Getting Started ====== | ====== Getting Started ====== | ||
Line 35: | Line 35: | ||
===== Required Hardware ===== | ===== Required Hardware ===== | ||
- | * [[http://www.xilinx.com/products/ | + | * [[xilinx>products/ |
* FMC-SDP adapter board | * FMC-SDP adapter board | ||
* **EVAL-ADF4002SD1Z** evaluation board | * **EVAL-ADF4002SD1Z** evaluation board | ||
Line 70: | Line 70: | ||
| **setregister=** | Update the selected latch with the current set ups. Accepted value:\\ latch:\\ 0 - Reference latch\\ 1 - N Counter Latch\\ 2 - Function Latch\\ 3 - Initialization Latch\\ value:\\ 24 bit values, you can find more information about the registers in the data sheet | | | **setregister=** | Update the selected latch with the current set ups. Accepted value:\\ latch:\\ 0 - Reference latch\\ 1 - N Counter Latch\\ 2 - Function Latch\\ 3 - Initialization Latch\\ value:\\ 24 bit values, you can find more information about the registers in the data sheet | | ||
| **getregister? | | **getregister? | ||
- | | **setfreq=** | Set the VCO frequency. Accepted value:\\ 5 .. 400 - betwwen 5Mhz and 400Mhz | | + | | **setfrequency=** | Set the VCO frequency. Accepted value:\\ 5 .. 400 - betwwen 5Mhz and 400Mhz | |
- | | **getfreq?** | Print the actual VCO frequency. | | + | | **getfrequency?** | Print the actual VCO frequency. | |
Commands can be executed using a serial terminal connected to the UART peripheral of Xilinx KC705 FPGA. | Commands can be executed using a serial terminal connected to the UART peripheral of Xilinx KC705 FPGA. |