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resources:fpga:xilinx:interposer:adf4001 [26 Mar 2012 17:19] – [More information] Alexandru.Tofan | resources:fpga:xilinx:interposer:adf4001 [09 Jan 2021 00:49] (current) – user interwiki links Robin Getz | ||
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===== Evaluation Boards ===== | ===== Evaluation Boards ===== | ||
- | * [[adi> | + | * [[adi>EVAL-ADF4001|EVAL-ADF4001SD1Z]] |
====== Overview ====== | ====== Overview ====== | ||
- | This document presents the steps to setup an environment for using the **[[adi> | + | This document presents the steps to setup an environment for using the **[[adi> |
{{ : | {{ : | ||
For component evaluation and performance purposes, as opposed to quick prototyping, | For component evaluation and performance purposes, as opposed to quick prototyping, | ||
- | * a controller board, like the **[[resources/ | + | * a controller board, like the **[[resources/ |
* a compatible Analog Devices SDP [[adi> | * a compatible Analog Devices SDP [[adi> | ||
* corresponding PC software | * corresponding PC software | ||
- | The EVAL-SDP-CB1Z controller board is part of Analog Devices SDP providing | + | The **EVAL-SDP-CS1Z** |
- | + | ||
- | Below is presented | + | |
- | + | ||
- | {{ : | + | |
The **EVAL-ADF4001SD1Z** is designed to allow the user to evaluate the perfor-mance of the ADF4001 frequency synthesizer for phase-locked loops (PLLs). Figure 1 shows the board, which contains the ADF4001 synthesizer, | The **EVAL-ADF4001SD1Z** is designed to allow the user to evaluate the perfor-mance of the ADF4001 frequency synthesizer for phase-locked loops (PLLs). Figure 1 shows the board, which contains the ADF4001 synthesizer, | ||
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* [[adi> | * [[adi> | ||
* [[adi>/ | * [[adi>/ | ||
- | * [[http://www.xilinx.com/products/ | + | * [[xilinx>products/ |
- | * [[http:// | + | |
====== Getting Started ====== | ====== Getting Started ====== | ||
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===== Required Hardware ===== | ===== Required Hardware ===== | ||
- | * [[http://www.xilinx.com/products/ | + | * [[xilinx>products/ |
* FMC-SDP adapter board | * FMC-SDP adapter board | ||
* **EVAL-ADF4001SD1Z** evaluation board | * **EVAL-ADF4001SD1Z** evaluation board | ||
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===== Required Software ===== | ===== Required Software ===== | ||
- | * Xilinx ISE 13.4 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack). | + | * Xilinx ISE 14.6. |
- | * [[http://micrium.com/ | + | * UART Terminal (Termite/Tera Term/Hyperterminal), |
===== Downloads ===== | ===== Downloads ===== | ||
+ | <WRAP round download 80%> | ||
+ | \\ | ||
+ | * **ADF4001 Driver:** https:// | ||
+ | * **ADF4001 Commands:** https:// | ||
+ | * **Xilinx Boards Common Drivers:** https:// | ||
+ | * **EDK KC705 Reference project:** https:// | ||
+ | \\ | ||
+ | </ | ||
- | * {{: | + | ===== Hardware setup ===== |
- | The following table presents a short description | + | <WRAP round important 80%> |
+ | \\ | ||
+ | Before connecting | ||
+ | </ | ||
- | ^ **Folder** ^ **Description** ^ | + | |
- | | Bit | Contains | + | * Connect |
- | | Microblaze | Contains the EDK 13.4 project for the Microblaze softcore that will be implemented in the KC705 FPGA. | | + | |
- | | Software | Contains the source files of the software project that will be run by the Microblaze processor.| | + | |
- | | uCProbeInterface | Contains | + | |
- | ====== Run the Demonstration | + | ===== Reference |
+ | The following commands were implemented in this version of EVAL-ADF4001SD1Z reference project for Xilinx KC705 FPGA board. | ||
+ | ^ Command ^ Description ^ | ||
+ | | **help?** | Displays all available commands. | | ||
+ | | **setregister=** | Update the selected latch with the current set ups. Accepted value:\\ latch:\\ 0 - Reference latch\\ 1 - N Counter Latch\\ 2 - Function Latch\\ 3 - Initialization Latch\\ value:\\ 24 bit values, you can find more information about the registers in the data sheet | | ||
+ | | **getregister? | ||
+ | | **setfrequency=** | Set the VCO frequency. Accepted value:\\ 5 .. 200 - betwwen 5Mhz and 200Mhz | | ||
+ | | **getfrequency? | ||
- | {{page> | + | Commands can be executed using a serial terminal connected to the UART peripheral of Xilinx KC705 FPGA. |
- | ===== Demonstration Project User Interface ===== | + | The following image shows a generic list of commands in a serial terminal connected to Xilinx KC705 FPGA's UART peripheral. |
+ | {{ : | ||
- | The following figure presents the **uC-Probe** interface that can be used for monitoring and controlling the operation of the **EVAL-ADF4001SD1Z** evaluation board. | + | ===== Software Project Setup ===== |
- | + | {{page> | |
- | {{ : | + | |
- | + | ||
- | The communication with the board is activated / deactivated by toggling the ON/OFF switch. The Activity LED turns green when the communication is active. Before pressing the Activity switch, make sure you select the desired Device Initialization procedure. If the ON/OFF switch is set to ON and the Activity LED is BLACK it means that there is a communication problem with the board. See the **Troubleshooting** section for indications on how to fix the communication problems. | + | |
- | + | ||
- | The Error LED will indicate that the data received on the SDO pin is different than data sent. If the Function Latch or Initialization Latch is written, with different MUXOUT value than 6, the LED will be activated. To reset the LED, the board must be deactivated and reactivated, | + | |
- | + | ||
- | The interface allows for configuring each latch on the ADF4001. After setting each bit to the desired value, by activating the Write switch the latch will be updated with the value displayed in the left most numeric display. | + | |
- | + | ||
- | ===== Troubleshooting | + | |
- | + | ||
- | In case there is a communication problem with the board the follwing actions can be perfomed in order to try to fix the issues: | + | |
- | * Check that the evaluation board is powered as instructed in the board' | + | |
- | * In uC-Probe refresh the symbols file by right-clicking on the **//System Browser//** window and selecting **//Refresh Symbols// | + | |
- | * If the communication problem persists even after performing the previous steps, restart the uC-Probe application and try to run the interface again. | + | |
====== More information ====== | ====== More information ====== | ||
- | * [[ez>community/ | + | {{page>ez_common}} |