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resources:fpga:xilinx:interposer:ad9833 [17 Feb 2012 18:13] – used ucprobe_common page to replace some sections Adrian Costina | resources:fpga:xilinx:interposer:ad9833 [09 Jan 2021 00:49] (current) – user interwiki links Robin Getz | ||
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====== Overview ====== | ====== Overview ====== | ||
- | This document presents the steps to setup an environment for using the **[[adi> | + | This document presents the steps to setup an environment for using the **[[adi> |
{{ : | {{ : | ||
- | For component evaluation and performance purposes, as opposed to quick prototyping, | + | {{page>common_sdp}} |
- | * a controller board, like the **[[resources/ | + | |
- | * a compatible Analog Devices SDP [[adi>sdp# | + | |
- | * corresponding PC software | + | |
- | The EVAL-SDP-CB1Z controller board is part of Analog Devices SDP providing USB 2.0 high-speed connectivity to a PC computer running specific component evaluation software. | + | |
Below is presented a picture of **SDP-B** Controller Board with the **EVAL-AD9833SDZ** Evaluation Board. | Below is presented a picture of **SDP-B** Controller Board with the **EVAL-AD9833SDZ** Evaluation Board. | ||
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* [[adi> | * [[adi> | ||
* [[adi>/ | * [[adi>/ | ||
- | * [[http://www.xilinx.com/products/ | + | * [[xilinx>products/ |
- | * [[http:// | + | |
====== Getting Started ====== | ====== Getting Started ====== | ||
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===== Required Hardware ===== | ===== Required Hardware ===== | ||
- | * [[http://www.xilinx.com/products/ | + | * [[xilinx>products/ |
* FMC-SDP adapter board | * FMC-SDP adapter board | ||
* **EVAL-AD9833** evaluation board | * **EVAL-AD9833** evaluation board | ||
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===== Required Software ===== | ===== Required Software ===== | ||
- | * Xilinx ISE 13.4 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack). | + | * Xilinx ISE 14.6. |
- | * [[http://micrium.com/ | + | * UART Terminal (Termite/Tera Term/Hyperterminal), |
+ | * The EVAL-AD9833 reference project for Xilinx KC705 FPGA. | ||
===== Downloads ===== | ===== Downloads ===== | ||
- | + | <WRAP round download 80%> | |
- | * {{:resources: | + | \\ |
- | + | * **AD9833 Driver:** https://github.com/ | |
- | The following table presents a short description the reference design archive contents. | + | * **AD9833 Commands:** https:// |
- | + | | |
- | ^ **Folder** ^ **Description** ^ | + | * **EDK KC705 Reference |
- | | Bit | Contains the KC705 configuration file that can be used to program the system for quick evaluation. | | + | \\ |
- | | Microblaze | Contains the EDK 13.4 project for the Microblaze softcore that will be implemented in the KC705 FPGA. | | + | </ |
- | | Software | Contains the source files of the software | + | |
- | | uCProbeInterface | Contains the uCProbe interface and the .elf symbols file used by uC-Probe to access data from the Microblaze memory. | | + | |
====== Run the Demonstration Project ====== | ====== Run the Demonstration Project ====== | ||
- | {{page> | + | ===== Hardware setup ===== |
- | ===== Demonstration Project User Interface ===== | + | <WRAP round important 80%> |
+ | \\ | ||
+ | Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage of the KC705 is set to 3.3V. For more details on how to change the setting for VADJ_FPGA visit the Xilinx KC705 product page. | ||
+ | </ | ||
- | The following figure presents | + | * Use the FMC-SDP interposer to connect the ADI evaluation board to the Xilinx KC705 board on the FMC LPC connector. |
+ | | ||
- | {{ :resources:fpga:altera:bemicro:ad9833interface.png?700 }} | + | ===== Reference Project Overview ===== |
+ | The following commands were implemented in this version of EVAL-AD9833 reference project for Xilinx KC705 FPGA board. | ||
+ | ^ Command ^ Description ^ | ||
+ | | **help?** | Displays all available commands. | | ||
+ | | **output=** | Selects the type of output. Accepted values:\\ 0 - Sinusoid.(default)\\ 1 - Triangle.\\ 2 - DAC Data MSB/2.\\ 3 - DAC Data MSB. | | ||
+ | | **output?** | Displays the type of output. | | ||
+ | | **loadFreqReg=** | Loads a frequency value in one selected register. Accepted values:\\ Register number:\\ 0 - Frequency Register 0.\\ 1 - Frequency Register 1.\\ Value:\\ 0 .. 12 500 000 - the frequency value in Hz. | | ||
+ | | **freqRegVal? | ||
+ | | **loadPhaseReg=** | Loads a phase value in one selected register. Accepted values:\\ Register number:\\ 0 - Phase Register 0.\\ 1 - Phase Register 1.\\ Value:\\ 0 .. 2PI - the phase value in radians. | | ||
+ | | **phaseRegVal?** | Displays the value from one selected phase register. | ||
+ | | **freqRegNo=** | Select the frequency register to be used. Accepted values:\\ Register number:\\ 0 - Frequency Register 0.\\ 1 - Frequency Register 1. | | ||
+ | | **freqRegNo? | ||
+ | | **phaseRegNo=** | Select the phase register to be used. Accepted values:\\ Register number:\\ 0 - Phase Register 0.\\ 1 - Phase Register 1. | | ||
+ | | **phaseRegNo? | ||
+ | | **sleepMode=** | Select one sleep mode. Accepted values:\\ Sleep mode:\\ 0 - No power-down.(default)\\ 1 - DAC powered down.\\ 2 - Internal clock disabled. \\ 3 - DAC powered down and Internal clock disabled. | | ||
+ | | **sleepMode? | ||
+ | |||
- | **Section A** is used to activate the board and monitor activity. The communication with the board is activated / deactivated by toggling the **// | + | Commands can be executed using a serial terminal connected |
- | **Section B** is used to choose the frequency register, the phase register and the signal from the VOUT output. | + | The following image shows a generic list of commands in a serial terminal connected |
+ | {{ : | ||
- | // | + | ===== Software Project Setup ===== |
- | * //F1// – FREQ1 register is used in the phase accumulator. | + | {{page> |
- | * //F0// – FREQ0 register is used in the phase accumulator. | + | |
- | + | ||
- | //**Phase control: | + | |
- | * //P1// – PHASE1 register data is added to the output of the phase accumulator. | + | |
- | * //P0// – PHASE0 register data is added to the output of the phase accumulator. | + | |
- | + | ||
- | //**VOUT Output: | + | |
- | * //MSB// – MSB of the DAC at the output. | + | |
- | * //MSB/2// – MSB/2 of the DAC at the output. | + | |
- | * // | + | |
- | * // | + | |
- | + | ||
- | **Section C** is used to load values in the frequency and phase registers. | + | |
- | A frequency value is set using the corresponding dial and slider controls. | + | |
- | + | ||
- | * put the dial to position 0 and move the slider to 4; | + | |
- | * put the dial to position 1 and move the slider to 3; | + | |
- | * put the dial to position 2 and move the slider to 2; | + | |
- | * put the dial to position 3 and move the slider to 1. | + | |
- | + | ||
- | **Section D** is used to select the sleep mode of the circuit. | + | |
- | + | ||
- | **Section E** is used to activate and control the Frequency Sweep function. | + | |
- | * //Sweep ON / Sweep OFF//: Turn ON / OFF the sweep function. | + | |
- | * //Start / Stop//: Start / Stop the sweep function. | + | |
- | * //Start Frequency//: | + | |
- | * //Stop Frequency//: | + | |
- | * //Step Frequency//: | + | |
- | * //Delay//: Value of the delay between each frequency increment. | + | |
- | + | ||
- | ===== Troubleshooting | + | |
- | + | ||
- | In case there is a communication problem with the board the follwing actions can be perfomed in order to try to fix the issues: | + | |
- | * Check that the evaluation board is powered as instructed in the board' | + | |
- | * In uC-Probe refresh the symbols file by right-clicking on the **//System Browser//** window and selecting **//Refresh Symbols// | + | |
- | * If the communication problem persists even after performing the previous steps, restart the uC-Probe application and try to run the interface again. | + | |
====== More information ====== | ====== More information ====== | ||
- | * [[ez> | + | * [[resources: |
+ | {{page> |