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resources:fpga:xilinx:interposer:ad9783 [30 Jan 2023 09:21] – Replaced the obsolete Kuiper Linux page link Joyce Velascoresources:fpga:xilinx:interposer:ad9783 [30 Jan 2023 18:17] (current) – Add details on how the constraints file was created Iulia Moldovan
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 ===== Functional Description ===== ===== Functional Description =====
 +
 +==== Block Diagram ====
 +
 The reference design consists of a DDS module and a LVDS interface.  The reference design consists of a DDS module and a LVDS interface. 
 {{ :resources:fpga:xilinx:interposer:ad9783_zcu102_bd.jpg?direct |}} {{ :resources:fpga:xilinx:interposer:ad9783_zcu102_bd.jpg?direct |}}
 +
 +==== Description ====
 +
 +=== Creating the constraints ====
 +
 +When creating the constraints file for this project, the AD9783-EBZ, AD-DAC-FMC-ADP and ZCU102 schematics were used, because we have to make a correspondence between the signals from one side and the other. \\
 +First, we look in the AD9783-EBZ schematic and we spot the signals we have to use in the HDL design, like D[15:0] LVDS pairs, DCI_P and _N, DCO_P and _N, and the SPI signals (SDIO, SDO, SCLK and CSB). \\
 +Then, we check which pins are their correspondents in the AD-DAC-FMC-ADP schematic. \\
 +
 +Example: \\
 +
 +**AD9783-EBZ schematic**: D15P is connected to J17 plug header, at A3 \\
 +**AD-DAC-FMC-ADP schematic**: J17 plug header pin A3 is called TXI_DATA_P15 and is connected to CLK1_M2C_P pin from P1 FMC header \\
 +**ZCU102 schematic**: pin CLK1_M2C_P is pin T8 in FMC HP0 \\
 +Thus we have this constraint: \\
 +<code>
 +set_property -dict {PACKAGE_PIN  T8 IOSTANDARD LVDS} [get_ports data_p[15]] ; ## G2 FMC_HPC0_CLK1_M2C_P
 +</code>
 +
 +
 +===== Quick Start Guide =====
  
 ==== Required Hardware ==== ==== Required Hardware ====
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   * An UART terminal, with baud rate 115200   * An UART terminal, with baud rate 115200
  
-===== Quick Start Guide =====+==== Setup ====
 {{ :resources:fpga:xilinx:interposer:ad9783_zcu102_setup.jpg?direct&600 |}} {{ :resources:fpga:xilinx:interposer:ad9783_zcu102_setup.jpg?direct&600 |}}
  
resources/fpga/xilinx/interposer/ad9783.txt · Last modified: 30 Jan 2023 18:17 by Iulia Moldovan

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