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resources:fpga:xilinx:interposer:ad9747 [27 Jun 2012 17:42] – [Registers] rejeesh kuttyresources:fpga:xilinx:interposer:ad9747 [12 Jun 2017 14:53] – Fix FMC link Lars-Peter Clausen
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 The [[adi>AD9747]] is a dual 16-bit, digital-to-analog converter (DAC) with gain and offset compensation. This reference design includes two DDS generators that drives both channels of the device. The programming is done via the USB-SPI interface. The reference design works with all the AD974x pin-compatible devices - AD9741(8bit), AD9743(10bit), AD9745(12bit), AD9746(14bit) and AD9747(16bit) - only the upper bits of the data lines are used for the various bit widths. The [[adi>AD9747]] is a dual 16-bit, digital-to-analog converter (DAC) with gain and offset compensation. This reference design includes two DDS generators that drives both channels of the device. The programming is done via the USB-SPI interface. The reference design works with all the AD974x pin-compatible devices - AD9741(8bit), AD9743(10bit), AD9745(12bit), AD9746(14bit) and AD9747(16bit) - only the upper bits of the data lines are used for the various bit widths.
  
-**HW Platform(s):** [[http://www.xilinx.com/kc705|Kintex-7 KC705 (Xilinx)]], [[http://www.analog.com/en/digital-to-analog-converters/da-converters/ad9747/products/EVAL-AD9747/eb.html|AD9747 Evaluation Board (ADI)]], [[http://www.analog.com/en/evaluation/ad-dac-fmc/eb.html|DAC FMC Interposer Board (ADI)]] \\ +===== Supported Devices ===== 
-**System:** Microblaze, AXI, UART+ 
 +  * [[http://www.analog.com/en/digital-to-analog-converters/da-converters/ad9747/products/EVAL-AD9747/eb.html|AD9747 Evaluation Board]] 
 +  * [[http://www.analog.com/en/evaluation/ad-dac-fmc/eb.html|DAC FMC Interposer Board]] 
 + 
 +===== Supported Carriers ===== 
 + 
 +  * [[xilinx> KC705]]  
 + 
  
 ===== Quick Start Guide ===== ===== Quick Start Guide =====
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 ==== Required Software ==== ==== Required Software ====
  
-  * Xilinx ISE 14.1 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack).+  * Xilinx ISE 14.4 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack).
   * A UART terminal (Tera Term/Hyperterminal), Baud rate 57600.   * A UART terminal (Tera Term/Hyperterminal), Baud rate 57600.
   * ADI DPG DAC Software Suite [[http://www.analog.com/en/digital-to-analog-converters/da-converters/products/evaluation-boardstools/CU_eb_DPG_high_speed_DAC_eval_platform/resources/fca.html|available here]].   * ADI DPG DAC Software Suite [[http://www.analog.com/en/digital-to-analog-converters/da-converters/products/evaluation-boardstools/CU_eb_DPG_high_speed_DAC_eval_platform/resources/fca.html|available here]].
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   * Connect two USB cables from the PC to the //JTAG// and //UART// USB connectors on KC705.   * Connect two USB cables from the PC to the //JTAG// and //UART// USB connectors on KC705.
   * Connect a USB cable to the AD9747-EBZ board.   * Connect a USB cable to the AD9747-EBZ board.
-  * Connect an external clock source to AD9747-EBZ board's J1 (CLOCK IN) SMA connector. Please refer to the schematic and the evaluation board quick start guide and make sure this is your clock source on board. The clock source may be J4 (DAC CLK) depending on JP2/JP3. +  * Connect an external clock source to AD9747-EBZ board's J1 (CLOCK IN) SMA connector. Please refer to the schematic and the evaluation board quick start guide and make sure this is your clock source on board. The clock source may be J4 (DAC CLK) depending on JP2/JP3. Setup the clock source to be 250MHz(2dBm)
   * Connect two spectrum analyzers to AD9747-EBZ board's J5 and J9 SMA connectors. Please refer to the schematic and the evaluation board quick start guide and make sure these are connected to the DAC outputs.    * Connect two spectrum analyzers to AD9747-EBZ board's J5 and J9 SMA connectors. Please refer to the schematic and the evaluation board quick start guide and make sure these are connected to the DAC outputs. 
  
-Setup the clock source to be 250MHz(2dBm). After the hardware setup, turn the power on to the KC705 and the AD9747-EBZ boards. If desired, change the VADJ on KC705 to 3.3v.+After the hardware setup, turn the power on to the KC705 and the AD9747-EBZ boards. If desired, change the VADJ on KC705 to 3.3v.
    
 {{:resources:fpga:xilinx:interposer:cf_ad9747_ebz_setup.jpg?200|Hardware setup}} {{:resources:fpga:xilinx:interposer:cf_ad9747_ebz_setup.jpg?200|Hardware setup}}
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 ===== Downloads ===== ===== Downloads =====
  
-{{:resources:fpga:xilinx:interposer:cf_ad9747_ebz.tar.gz|Reference Design Source Code}}+FPGA Referece Designs: 
 +<WRAP round download 80%> 
 +  * **KC705 (Source files)** {{:resources:fpga:xilinx:interposer:cf_ad9747_ebz_edk_14_4_2013_03_15.tar.gz}} 
 +  * **KC705 (Quick start bit files)** {{:resources:fpga:xilinx:interposer:cf_ad9747_ebz_sw_14_4_2013_03_15.tar.gz}} 
 +</WRAP>
  
-===== Notes =====+Only Xilinx coregen xco files are provided with the reference design. You must regenerate the IP core files using this file. See [[http://wiki.analog.com/resources/eval/user-guides/ad-fmcomms1-ebz/reference_hdl|generating Xilinx netlist/verilog files from xco files]] for details.
  
-The following two files are missing from the tar file.+<WRAP round help 80%> 
 +  * Questions? [[http://ez.analog.com/post!input.jspa?containerType=14&container=2061|Ask Help & Support]]. 
 +</WRAP>
  
-  * cf_lib/edk/pcores/axi_ad9747_v1_00_a/netlist/cf_ddsx_1.ngc 
-  * cf_lib/edk/pcores/axi_ad9747_v1_00_a/hdl/verilog/cf_ddsx_1.v 
  
-To use the reference design as it is, re-generate these two files (16bit full-range sine DDS). 
  
 ===== Tar file contents ===== ===== Tar file contents =====
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 ===== More information ===== ===== More information =====
  
-  * [[http://www.vita.com/fmc.html|VITA's FMC info]]+  * [[http://www.vita.com/fmc|VITA's FMC info]]
   * [[ez>community/fpga|Ask questions about the FPGA reference design]]   * [[ez>community/fpga|Ask questions about the FPGA reference design]]
  
  
  
resources/fpga/xilinx/interposer/ad9747.txt · Last modified: 28 Jan 2021 19:14 by Robin Getz

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