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resources:fpga:xilinx:interposer:ad9739a [08 Mar 2013 20:32] – [Notes] rejeesh kuttyresources:fpga:xilinx:interposer:ad9739a [28 Jan 2021 19:14] – update arrow links after their web site update Robin Getz
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 ===== Supported Devices ===== ===== Supported Devices =====
  
-  * [[http://www.analog.com/en/digital-to-analog-converters/da-converters/ad9739a/products/EVAL-AD9739A/eb.html|AD9739A Evaluation Board]] +  * [[adi>en/digital-to-analog-converters/da-converters/ad9739a/products/EVAL-AD9739A/eb.html|AD9739A Evaluation Board]] 
-  * [[http://www.analog.com/en/digital-to-analog-converters/da-converters/ad-dac-fmc/products/product.html|DAC FMC Interposer Board]]+  * [[adi>en/evaluation/ad-dac-fmc/eb.html|DAC FMC Interposer Board]]
  
  
 ===== Supported Carriers ===== ===== Supported Carriers =====
  
-  * [[xilinx> ML605]]  +  * [[xilinx>ML605]]  
-  * [[xilinx> KC705]]  +  * [[xilinx>KC705]]  
-  * [[xilinx> VC707]] +  * [[xilinx>VC707]] 
  
  
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   * Xilinx ISE 13.2 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack).   * Xilinx ISE 13.2 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack).
   * A UART terminal (Tera Term/Hyperterminal), Baud rate 57600.   * A UART terminal (Tera Term/Hyperterminal), Baud rate 57600.
-  * ADI DPG DAC Software Suite [[http://www.analog.com/en/digital-to-analog-converters/da-converters/products/evaluation-boardstools/CU_eb_DPG_high_speed_DAC_eval_platform/resources/fca.html|available here]].+  * ADI DPG DAC Software Suite [[/resources/eval/dpg/dacsoftwaresuite|available here]].
  
 ==== Bit file ==== ==== Bit file ====
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 </WRAP> </WRAP>
  
-Only Xilinx coregen xco files are provided with the reference design. You must regenerate the IP core files using this file. See [[http://wiki.analog.com/resources/eval/user-guides/ad-fmcomms1-ebz/reference_hdl|generating Xilinx netlist/verilog files from xco files]] for details.+Only Xilinx coregen xco files are provided with the reference design. You must regenerate the IP core files using this file. See [[/resources/eval/user-guides/ad-fmcomms1-ebz/reference_hdl|generating Xilinx netlist/verilog files from xco files]] for details.
  
 <WRAP round help 80%> <WRAP round help 80%>
-  * Questions? [[http://ez.analog.com/post!input.jspa?containerType=14&container=2061|Ask Help & Support]].+  * Questions? [[ez>community/fpga|Ask Help & Support]].
 </WRAP> </WRAP>
  
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 ===== Tar file contents ===== ===== Tar file contents =====
  
-The tar file contains, in most cases, the following files and/or directories. To rebuild the reference design simply double click the XMP file and run the tool. To build SDK, select a workspace and use the C file to build the elf file. Please refer to [[http://www.xilinx.com/support/documentation/dt_edk_edk13-2.htm|Xilinx EDK documentation]] for details.+The tar file contains, in most cases, the following files and/or directories. To rebuild the reference design simply double click the XMP file and run the tool. To build SDK, select a workspace and use the C file to build the elf file. Please refer to [[xilinx>support/documentation/dt_edk_edk13-2.htm|Xilinx EDK documentation]] for details.
  
 | license.txt | ADI license & copyright information. | | license.txt | ADI license & copyright information. |
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 ===== More information ===== ===== More information =====
  
-  * [[http://www.vita.com/fmc.html|VITA's FMC info]]+  * [[http://www.vita.com/fmc|VITA's FMC info]]
   * [[ez>community/fpga|Ask questions about the FPGA reference design]]   * [[ez>community/fpga|Ask questions about the FPGA reference design]]
  
  
  
resources/fpga/xilinx/interposer/ad9739a.txt · Last modified: 20 Dec 2023 11:50 by Stefan-Robert Raus

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