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resources:fpga:xilinx:interposer:ad9683 [03 Jan 2021 22:12]
Robin Getz fix links
resources:fpga:xilinx:interposer:ad9683 [25 Jan 2021 19:33]
Robin Getz update renesas links after their web site update
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 </​WRAP>​ </​WRAP>​
  
-Only Xilinx coregen xco files are provided with the reference design. You must regenerate the IP core files using this file. See [[http://​wiki.analog.com/​resources/​eval/​user-guides/​ad-fmcomms1-ebz/​reference_hdl|generating Xilinx netlist/​verilog files from xco files]] for details.+Only Xilinx coregen xco files are provided with the reference design. You must regenerate the IP core files using this file. See [[/​resources/​eval/​user-guides/​ad-fmcomms1-ebz/​reference_hdl|generating Xilinx netlist/​verilog files from xco files]] for details.
  
 <WRAP round help 80%> <WRAP round help 80%>
-  * Questions? [[http://ez.analog.com/​post!input.jspa?​containerType=14&​container=2061|Ask Help & Support]].+  * Questions? [[ez>fpga|Ask Help & Support]].
 </​WRAP>​ </​WRAP>​
  
 ===== Tar file contents ===== ===== Tar file contents =====
  
-The tar file contains, in most cases, the following files and/or directories. To rebuild the reference design simply double click the XMP file and run the tool. To build SDK, select a workspace and use the C file to build the elf file. Please refer to [[http://www.xilinx.com/support/​documentation/​dt_edk_edk13-2.htm|Xilinx EDK documentation]] for details.+The tar file contains, in most cases, the following files and/or directories. To rebuild the reference design simply double click the XMP file and run the tool. To build SDK, select a workspace and use the C file to build the elf file. Please refer to [[xilinx>support/​documentation/​dt_edk_edk13-2.htm|Xilinx EDK documentation]] for details.
  
 | license.txt | ADI license & copyright information. | | license.txt | ADI license & copyright information. |
resources/fpga/xilinx/interposer/ad9683.txt · Last modified: 28 Jan 2021 19:14 by Robin Getz