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The AD9671 is designed for low cost, low power, small size, and ease of use for medical ultrasound. It contains eight channels of a variable gain amplifier (VGA) with a low noise preamplifier (LNA), a CW harmonic rejection I/Q demodulator with programmable phase rotation, an anti-aliasing filter (AAF), an analog-to-digital converter (ADC), and a digital demodulator and decimator for data processing and bandwidth reduction. This reference design includes the device data capture via the JESD204B serial interface. The samples are written to the external DDR-DRAM on KC705. It allows programming the device and monitoring it's internal registers via SPI.
The reference design zip file contains a bit file combined with a SDK elf file for a quick demonstration of the programming and data capture. All you need is the hardware and a PC running a UART terminal and the programmer (IMPACT).
Please do the following modifications on the AD9671 evaluation board (9671EE01B).
The board uses a 40MHz external clock for the ADC and the JESD reference clock. The GTX is setup to use a 80MHz reference clock (can not run less than 60MHz). The solution is to use a 80MHz external clock input to the board. This clock is then passed to the GTX as the reference clock and AD9517 to generate a 40MHz clock for the ADC.
To begin make the following connections (see image below):
The quick start bit file configures the AD9671 for all test modes and verifies the captured data accordingly. After the hardware setup, turn the power on to the KC705 and the AD9671-EBZ boards.
Start IMPACT, and initialze the JTAG chain. The program should recognize the Kintex 7 device. Start a UART terminal (set to 57600 baud rate) and then program the device. If programming was successful, you should be seeing messages appear on the terminal as shown in figure below. The program asks for either “real 4 lane” mode or “complex 4 lane” mode. The complex mode is not supported yet. To test the real mode, enter 'r' on the uart terminal. After programming the AD9671, the program checks data capture on various test modes.
After patterns and prbs sequences are verified, if no errors are present, you may use the chipscope busplot to see the captured signal (see below). The ADC data is available on pins [127:0] of UNIT:1 with sets of 16bits for each channel.
The reference design is built on a microblaze based system parameterized for linux. A functional block diagram of the design is given below.
The reference design consists of two pcores. The JESD core consists of the GTX units and the Xilinx JESD 204 IP core. The AD9671 core consists of three functional modules, the ADC interface, a PN9/PN23 monitor and a DMA interface. The ADC interface captures and buffers data from the JESD core. The DMA interface then transfers the samples to the external DDR-DRAM. The capture is initiated by the software. The status of capture (overflow, over the range) are reported back to the software.
The JESD core and AD9671 core has an AXI lite interface that allows control and monitoring of the capture process.
Please refer to the regmap.txt file in the pcores directory.
FPGA Referece Designs:
Only Xilinx coregen xco files are provided with the reference design. You must regenerate the IP core files using this file. See generating Xilinx netlist/verilog files from xco files for details.
The tar file contains, in most cases, the following files and/or directories. To rebuild the reference design simply double click the XMP file and run the tool. To build SDK, select a workspace and use the C file to build the elf file. Please refer to Xilinx EDK documentation for details.
|license.txt||ADI license & copyright information.|
|system.xmp||XMP file (use this file to build the reference design).|
|data/||UCF file and/or DDR MIG project files.|
|docs/||Documentation files (Please note that this wiki page is the documentation for the reference design).|
|sw/||Software (Xilinx SDK) & bit file(s).|
|cf_lib/edk/pcores/||Reference design core file(s) (Xilinx EDK).|