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resources:fpga:xilinx:interposer:ad9467 [16 Jul 2015 10:51] – [Supported Carriers] Lucian Sinresources:fpga:xilinx:interposer:ad9467 [25 Apr 2023 10:56] – Separate obsolete section Iulia Moldovan
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 ====== AD9467 Evaluation Board, ADC-FMC Interposer & Xilinx Reference Design ====== ====== AD9467 Evaluation Board, ADC-FMC Interposer & Xilinx Reference Design ======
    
 +This wiki page contains sections with obsolete information, but are kept for legacy purposes. Pay attention to the "OBSOLETE" text in bold.
 +
 ===== Introduction ===== ===== Introduction =====
  
 The [[adi>AD9467]] is a 16-bit, monolithic, IF sampling analog-to-digital converter (ADC) with a conversion rate of up to 250MSPS. This reference design includes the device data capture and SPI interface. The samples are written to the external DDR-DRAM on ML605. It allows programming the device and monitoring its internal registers via SPI. It also allows programming the [[adi>AD9517-4]] clock chip as an alternative clock source on the board. The board also provides other options to drive the clock to the ADC. The [[adi>AD9467]] is a 16-bit, monolithic, IF sampling analog-to-digital converter (ADC) with a conversion rate of up to 250MSPS. This reference design includes the device data capture and SPI interface. The samples are written to the external DDR-DRAM on ML605. It allows programming the device and monitoring its internal registers via SPI. It also allows programming the [[adi>AD9517-4]] clock chip as an alternative clock source on the board. The board also provides other options to drive the clock to the ADC.
  
-===== Supported Devices =====+===== Supported devices =====
  
-  * [[http://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/EVAL-AD9467.html#eb-overview|AD9467 Evaluation Board]] +  * [[adi>en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/EVAL-AD9467.html#eb-overview|AD9467 Evaluation Board]] 
-  * [[http://www.analog.com/en/evaluation/eval-adc-fmc-int/eb.html | ADC-FMC Interposer A]]+  * [[adi>en/evaluation/eval-adc-fmc-int/eb.html | ADC-FMC Interposer A]] 
 + 
 +===== Supported carriers ===== 
 + 
 +  * [[xilinx>KC705]] 
 +  * [[https://www.avnet.com/wps/portal/us/products/avnet-boards/avnet-board-families/zedboard/ | ZedBoard]] 
 +  * [[xilinx>ML605]] (check Obsolete Quick Start Guide) 
 +  * [[xilinx>VC707]] (check Obsolete Quick Start Guide) 
 + 
 +===== Quick start guide ===== 
 + 
 +==== Required hardware ==== 
 + 
 +==== Required software ==== 
 + 
 +  * ZedBoard or KC705 board 
 +  * AD9467-FMC-250EBZ 
 +  * Signal/clock generator (clock input, 200MHz or 250MHz) 
 +  * Signal generator (analog input, for data capture) 
 +  * UART terminal (Tera Term/Putty), Baud rate 57600
  
-===== Supported Carriers =====+==== Hardware modifications ====
  
-  * [[xilinx>ML605]]  +===== Obsolete quick start guide =====
-  * [[xilinx>KC705]]  +
-  * [[xilinx>VC707]] +
  
 +This quick start guide is kept for legacy purposes only, and the designs on carriers ML605 and VC707 are no longer supported.
  
-===== Quick Start Guide =====+++++ Click to expand Obsolete Quick Start Guide |
  
 The reference design has been tested with ML605, KC705 and VC707. The notes below refer to ML605, the procedure is same for the other boards. Please make sure you are using the correct reference design for the board(s) that you have. The bit file provided combines the FPGA bit file and the SDK elf files. It may be used for a quick check on the system. All you need is the hardware and a PC running a UART terminal and the programmer (IMPACT).  The reference design has been tested with ML605, KC705 and VC707. The notes below refer to ML605, the procedure is same for the other boards. Please make sure you are using the correct reference design for the board(s) that you have. The bit file provided combines the FPGA bit file and the SDK elf files. It may be used for a quick check on the system. All you need is the hardware and a PC running a UART terminal and the programmer (IMPACT). 
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 ==== Required Hardware ==== ==== Required Hardware ====
  
-  * ML605, KC705 or VC707 board +  * ML605, KC705 or VC707 board
   * AD9467-2x0EBZ board & Power supply   * AD9467-2x0EBZ board & Power supply
   * ADC FMC interposer board   * ADC FMC interposer board
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   * Xilinx ISE 13.2 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack).   * Xilinx ISE 13.2 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack).
-  * A UART terminal (Tera Term/Hyperterminal), Baud rate 57600.+  * UART terminal (Tera Term/Hyperterminal), Baud rate 57600.
  
 ==== Bit file ==== ==== Bit file ====
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 The reference design is built on a microblaze based system parameterized for linux. A functional block diagram of the design is given below. The reference design is built on a microblaze based system parameterized for linux. A functional block diagram of the design is given below.
  
-{{:resources:fpga:xilinx:interposer:cf_ad9467_ebz_bd.jpg?400|block diagram}}+=== Xilinx block diagram === 
 +{{:resources:fpga:xilinx:fmc:ad9467_ebz:ad9467_fmc.svg?500|Xilinx HDL Block Diagram}} 
 + 
 +=== AD9467 FMC Card block diagram === 
 +{{:resources:fpga:xilinx:fmc:ad9467_ebz:ad9467_fmc_card.svg?400|Xilinx HDL Block Diagram}}
  
 The reference design consists of three functional modules, a LVDS interface, a PN9/PN23/PAT monitor and a DMA interface.  The reference design consists of three functional modules, a LVDS interface, a PN9/PN23/PAT monitor and a DMA interface. 
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 </WRAP> </WRAP>
  
-Only Xilinx coregen xco files are provided with the reference design. You must regenerate the IP core files using this file. See [[http://wiki.analog.com/resources/eval/user-guides/ad-fmcomms1-ebz/reference_hdl|generating Xilinx netlist/verilog files from xco files]] for details.+Only Xilinx coregen xco files are provided with the reference design. You must regenerate the IP core files using this file. See [[/resources/eval/user-guides/ad-fmcomms1-ebz/reference_hdl|generating Xilinx netlist/verilog files from xco files]] for details.
  
-<WRAP round help 80%> 
-  * Questions? [[http://ez.analog.com/post!input.jspa?containerType=14&container=2061|Ask Help & Support]]. 
-</WRAP> 
  
 ===== Tar file contents ===== ===== Tar file contents =====
  
-The tar file contains, in most cases, the following files and/or directories. To rebuild the reference design simply double click the XMP file and run the tool. To build SDK, select a workspace and use the C file to build the elf file. Please refer to [[http://www.xilinx.com/support/documentation/dt_edk_edk13-2.htm|Xilinx EDK documentation]] for details.+The tar file contains, in most cases, the following files and/or directories. To rebuild the reference design simply double click the XMP file and run the tool. To build SDK, select a workspace and use the C file to build the elf file. Please refer to [[xilinx>support/documentation/dt_edk_edk13-2.htm|Xilinx EDK documentation]] for details.
  
 | license.txt | ADI license & copyright information. | | license.txt | ADI license & copyright information. |
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 | cf_lib/edk/pcores/     | Reference design core file(s) (Xilinx EDK). | | cf_lib/edk/pcores/     | Reference design core file(s) (Xilinx EDK). |
  
 +++++
  
 ===== More information ===== ===== More information =====
  
-  * [[http://www.vita.com/fmc.html|VITA's FMC info]]+  * [[http://www.vita.com/|VITA's FMC info]]
   * [[ez>community/fpga|Ask questions about the FPGA reference design]]   * [[ez>community/fpga|Ask questions about the FPGA reference design]]
- 
- 
- 
resources/fpga/xilinx/interposer/ad9467.txt · Last modified: 25 Apr 2023 15:34 by Iulia Moldovan

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