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resources:fpga:xilinx:interposer:ad9279 [23 May 2012 22:32] – Add Atom feed Robin Getzresources:fpga:xilinx:interposer:ad9279 [11 May 2021 09:46] (current) – [Required Hardware] Meriam Yuson-Aguila
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-====== AD9279 FMC Interposer & Evaluation Board / Xilinx Reference Design ======+====== AD9279 Evaluation Board, ADC-FMC Interposer & Xilinx ML605 Reference Design ======
    
 ===== Introduction ===== ===== Introduction =====
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 The [[adi>AD9279]] is an eight channel variable gain amplifier (VGA) with a low noise preamplifier (LNA), an antialiasing filter (AAF), an analog-to-digital converter (ADC) and an I/Q demodulator with programmable phase rotation. It is a low cost, low power, small size device for applications in medical ultrasound and automotive radar. This reference design includes the device data capture and SPI interface. The samples are written to the external DDR-DRAM on ML605. It allows programming the device and monitoring it's internal registers via SPI. The reference design is based on ML605. The [[adi>AD9279]] is an eight channel variable gain amplifier (VGA) with a low noise preamplifier (LNA), an antialiasing filter (AAF), an analog-to-digital converter (ADC) and an I/Q demodulator with programmable phase rotation. It is a low cost, low power, small size device for applications in medical ultrasound and automotive radar. This reference design includes the device data capture and SPI interface. The samples are written to the external DDR-DRAM on ML605. It allows programming the device and monitoring it's internal registers via SPI. The reference design is based on ML605.
  
-**HW Platform:** [[http://www.xilinx.com/ml605|Virtex-6 ML605 (Xilinx)]], AD9279-EBZ customer evaluation board (ADI) and the ADC FMC Interposer Board (ADI) \\ +===== Supported Devices ===== 
-**System:** Microblaze, AXI, UART+ 
 +  * [[adi>AD9279-65EBZ|AD9279-65EBZ customer evaluation board]] 
 +  * [[adi>en/evaluation/eval-adc-fmc-int/eb.html| ADC FMC Interposer board]] 
 + 
 +===== Supported Carriers ===== 
 + 
 +  * [[xilinx>ML605]]  
  
 ===== Quick Start Guide ===== ===== Quick Start Guide =====
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   * ML605 board    * ML605 board 
   * AD9279-EBZ board & Power supply   * AD9279-EBZ board & Power supply
 +    *{{ :resources:fpga:xilinx:interposer:ad9279-ebz.pdf |}}- evaluation board schematic
   * ADC FMC interposer board   * ADC FMC interposer board
 +  * Signal generator (clock, optional)
   * Signal generator (analog input, for data capture)   * Signal generator (analog input, for data capture)
  
 ==== Required Software ==== ==== Required Software ====
  
-  * Xilinx ISE 13.2 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack).+  * Xilinx ISE 14.1 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack).
   * A UART terminal (Tera Term/Hyperterminal), Baud rate 57600.   * A UART terminal (Tera Term/Hyperterminal), Baud rate 57600.
  
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 ==== Running Demo (SDK) Program ==== ==== Running Demo (SDK) Program ====
- 
-<note tip>If you are not familiar with ML605 and/or Xilix tools, please visit\\ [[http://www.xilinx.com/ml605]] for details.</note> 
  
 To begin make the following connections (see image below): To begin make the following connections (see image below):
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   * Connect power to ML605 and the AD9279-EBZ boards.   * Connect power to ML605 and the AD9279-EBZ boards.
   * Connect two USB cables from the PC to the //JTAG// and //UART// USB connectors on ML605.   * Connect two USB cables from the PC to the //JTAG// and //UART// USB connectors on ML605.
-  * Connect a signal generator to channel A SMA connector.+  * The board uses a 65MHz oscillator (OSC501) as the clock source. If using an external clock source, remove R503, set jumper J501 to the OFF position and connect a clock source to J503. Set the clock source to 80MHz/0dBm. 
 +  * Connect a signal generator to channel A SMA connector. Set the signal source to 6MHz/-3dBm. 
 + 
 +{{:resources:fpga:xilinx:interposer:cf_ad9279_ebz_setup.jpg?200|Hardware setup}}
  
 After the hardware setup, turn the power on to the ML605 and the AD9467-2x0EBZ boards. Start IMPACT, and initialze the JTAG chain. The program should recognize the Virtex 6 device (see screenshot below). Start a UART terminal (set to 57600 baud rate) and then program the device. After the hardware setup, turn the power on to the ML605 and the AD9467-2x0EBZ boards. Start IMPACT, and initialze the JTAG chain. The program should recognize the Virtex 6 device (see screenshot below). Start a UART terminal (set to 57600 baud rate) and then program the device.
- 
-{{:resources:fpga:xilinx:interposer:cf_ad9279_ebz_impact.jpg?200|IMPACT}} 
  
 If programming was successful, you should be seeing messages appear on the terminal as shown in figure below. After programming the AD9279, the program checks data capture on various test modes. If programming was successful, you should be seeing messages appear on the terminal as shown in figure below. After programming the AD9279, the program checks data capture on various test modes.
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 {{:resources:fpga:xilinx:interposer:cf_ad9279_ebz_uart.jpg?200|Terminal}} {{:resources:fpga:xilinx:interposer:cf_ad9279_ebz_uart.jpg?200|Terminal}}
  
-After patterns and prbs sequences are verified, if no errors are present, you may use the chipscope busplot to see the captured signal (see below). The ADC data is available on pins [23:12] of the chipscope signal.+After patterns and prbs sequences are verified, if no errors are present, you may use the chipscope busplot to see the captured signal (see below). The ADC data is available on pins [11:0] of the chipscope signal. Individual channels may be enabled through the processor. The reference design runs internally at 160MHz, so two samples will appear on chipscope for default capture of the signal. The capture may be qualified with the internal data select signal (set trigger to 0x01 as the storage condition).
  
-{{:resources:fpga:xilinx:interposer:cf_ad9279_ebz_chipscope.jpg?200|Chipscope Busplot}}+Chipscope capture (raw):\\
  
-===== Using the reference design =====+{{:resources:fpga:xilinx:interposer:cf_ad9279_ebz_chipscope_1.jpg?200|Chipscope Busplot (raw)}}
  
-The reference design is built on a microblaze based system parameterized for linux. A functional block diagram of the design is given below.+Chipscope capture (storage qualified):\\
  
-{{:resources:fpga:xilinx:interposer:cf_ad9279_ebz_bd.jpg?400|block diagram}}+{{:resources:fpga:xilinx:interposer:cf_ad9279_ebz_chipscope_2.jpg?200|Chipscope Busplot (qualified)}}
  
-The reference design consists of three functional modules, a LVDS interface, a PN9/PN23/PAT monitor and a DMA interface. +===== Using the reference design =====
  
-The LVDS interface captures and buffers data from the ADC. The DMA interface then transfers the samples to the external DDR-DRAM. The capture is initiated by the software. The status of capture (overflow, over the range) are reported back to the software.+The reference design is built on a microblaze based system parameterized for linux. The reference design consists of three functional modules, a LVDS interface, a PN9/PN23/PAT monitor and a DMA interface. 
  
 +The LVDS interface captures and buffers data from the ADC. The DMA interface then transfers the samples to the external DDR-DRAM. The capture is initiated by the software. The status of capture (overflow, over the range) are reported back to the software.
  
 ==== Registers ==== ==== Registers ====
-^ QW Address<sup>1</sup> ^ Bits ^ Name ^ Description ^ + 
-| 0x00 | 31 | version | 32'h00_01_00_61 | +Please refer to the regmap.txt file inside pcores.
-| 0x03 | 16 | ADC capture start | ADC capture start (a 0x0 to 0x1 initiates start). | +
-|      | 15:0 | ADC capture count | ADC capture count (total count - 1). | +
-| 0x04 | 2 | DMA underflow | DMA underflow (W1C). | +
-|      | 1 | DMA overflow | DMA overflow (W1C). | +
-|      | 0 | DMA status | DMA idle (0x0) or busy (0x1) status. | +
-| 0x05 | 0 | PN errors | Spurious sequence mismatches in sync state (OOS == 0). | +
-|      | 0 | PN OOS | If sequence matches for 16 consecutive samples, OOS is cleared. If mismatch occurs for 64 consecutive samples, OOS is set. | +
-|      | 0 | ADC OR | ADC OR (W1C). | +
-| 0x06 | 31:0 | ADC sample | ADC captured sample (debug purposes only). | +
-| 0x09 | 7:0  | PN Type | PN9 (0x0) or PN23 (0x1). | +
-| 0x0a | 0 | ADC capture select | If data pattern mismatch occurs try setting this bit (see notes below) | +
-| 1. For AXI-Lite byte addresses, multiply by 4. |||| +
-| 2. All registers defaults to 0x0, unless otherwise specified. ||||+
  
 ==== Good To Know ==== ==== Good To Know ====
  
 The PN23 sequence is inverted, PN9 is not inverted. The PN23 sequence is inverted, PN9 is not inverted.
-  
  
 ===== Downloads ===== ===== Downloads =====
 +FPGA Referece Designs:
 +<WRAP round download 80%>
 +  * **ML605 (source files)** {{:resources:fpga:xilinx:interposer:cf_ad9279_ebz_edk_14_4_2013_03_26.tar.gz}}
 +  * **ML605 (bit/sw files)** {{:resources:fpga:xilinx:interposer:cf_ad9279_ebz_sw_14_4_2013_03_26.tar.gz}}
 +</WRAP>
 +
 +Only Xilinx coregen xco files are provided with the reference design. You must regenerate the IP core files using this file. See [[/resources/eval/user-guides/ad-fmcomms1-ebz/reference_hdl|generating Xilinx netlist/verilog files from xco files]] for details.
  
-{{:resources:fpga:xilinx:interposer:cf_ad9279_ebz.tar.gz|ML605 Reference Design Source Code}}\\+<WRAP round help 80%> 
 +  * Questions? [[ez>fpga|Ask Help & Support]]. 
 +</WRAP>
  
  
 ===== Tar file contents ===== ===== Tar file contents =====
  
-The tar file contains, in most cases, the following files and/or directories. To rebuild the reference design simply double click the XMP file and run the tool. To build SDK, select a workspace and use the C file to build the elf file. Please refer to [[http://www.xilinx.com/support/documentation/dt_edk_edk13-2.htm|Xilinx EDK documentation]] for details.+The tar file contains, in most cases, the following files and/or directories. To rebuild the reference design simply double click the XMP file and run the tool. To build SDK, select a workspace and use the C file to build the elf file. Please refer to [[xilinx>support/documentation/dt_edk_edk13-2.htm|Xilinx EDK documentation]] for details.
  
 | license.txt | ADI license & copyright information. | | license.txt | ADI license & copyright information. |
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 ===== More information ===== ===== More information =====
  
-  * [[http://www.vita.com/fmc.html|VITA's FMC info]] +  * [[http://www.vita.com/fmc|VITA's FMC info]] 
-  * [[ez>community/fpga|ask questions about the FPGA reference design]]+  * [[ez>community/fpga|Ask questions about the FPGA reference design]]
     * Example questions: {{rss>http://ez.analog.com/community/feeds/allcontent/atom?community=2061 5 author 1d}}     * Example questions: {{rss>http://ez.analog.com/community/feeds/allcontent/atom?community=2061 5 author 1d}}
resources/fpga/xilinx/interposer/ad9279.1337805163.txt.gz · Last modified: 23 May 2012 22:32 by Robin Getz

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