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--- resources:fpga:xilinx:interposer:ad9250 [28 Nov 2012 20:59] – [Downloads] rejeesh kutty
+++ resources:fpga:xilinx:interposer:ad9250 [20 Jan 2021 08:11] (current) – fix link Michael Hennerich
@@ Line 1: / Line 1: @@
-====== AD9250 Evaluation Board, ADC-FMC Interposer & Xilinx KC705 Reference Design ======
+====== AD9250 Evaluation Board, ADC-FMC Interposer & Xilinx Reference Design ======
 ===== Introduction =====
-The [[adi>AD9250]] is a dual, 14-bit ADC with sampling speeds of up to 250 MSPS. It is designed to support communications applications where low cost, small size, wide bandwidth and versatility are desired. The ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. This reference design includes the device data capture via the JESD204B serial interface and the SPI interface. The samples are written to the external DDR-DRAM on KC705. It allows programming the device and monitoring it's internal registers via SPI.
+The [[adi>AD9250]] is a dual, 14-bit ADC with sampling speeds of up to 250 MSPS. It is designed to support communications applications where low cost, small size, wide bandwidth and versatility are desired. The ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. This reference design includes the device data capture via the JESD204B serial interface and the SPI interface. The samples are written to the external DDR-DRAM on the carrier. It allows programming the device and monitoring its internal registers via SPI.
+A native FMC card with the [[adi>AD9250]] can be found [[../fmc/ad-fmcjesdadc1-ebz|FMCJESDADC1 Board]]
+===== Supported Devices =====
+  * [[adi>en/analog-to-digital-converters/ad-converters/ad9250/products/EVAL-AD9250/eb.html|AD9250 Evaluation Board]]
+  * [[adi>en/evaluation/EVAL-ADC-FMC-INT/eb.html|ADC FMC Interposer Board]]
+{{:resources:fpga:xilinx:fmc:ad9250_ebz:ad9250-ebz.jpg|AD9250}}
+===== Supported Carriers =====
+  * [[xilinx>KC705]]
+  * [[xilinx>VC707]]
+  * [[xilinx>ZC706]]
-**HW Platform(s):** [[http://www.xilinx.com/kc705|Kintex-7 KC705 (Xilinx)]], [[http://www.analog.com/en/analog-to-digital-converters/ad-converters/ad9250/products/EVAL-AD9250/eb.html|AD9250 Evaluation Board (ADI)]],  ADC FMC Interposer Board (ADI) \\
-**System:** Microblaze, AXI, UART
 ===== Quick Start Guide =====
-The reference design zip file contains a bit file combined with a SDK elf file for a quick demonstration of the programming and data capture. All you need is the hardware and a PC running a UART terminal and the programmer (IMPACT).
+The reference design zip file contains a bit file and a SDK elf file for a quick demonstration of the programming and data capture. The reference design has been tested with KC705, VC707 and ZC706. The notes below refer to KC705, the procedure is same for the other boards. Please make sure you are using the correct reference design for the board(s) that you have.
 ==== Required Hardware ====
-  * KC705 board
+  * KC705/VC707/ZC706 board
   * AD9250-EBZ board & Power supply (AD9250-250EBZ, AD9250-170EBZ)
   * ADC FMC interposer board (CVT-ADC-FMC-INTPZB)
@@ Line 22: / Line 35: @@
 ==== Required Software ====
-  * Xilinx ISE (Programmer (IMPACT) is sufficient for the demo and is available on Webpack).
+  * Xilinx ISE Design Suite 14.4
-  * A UART terminal (Tera Term/Hyperterminal), Baud rate 57600.
+  * A UART terminal (Tera Term/Hyperterminal), Baud rate 57600 (115200 for ZC706).
-==== Bit file ====
-  * Download the gzip file and extract the **sw/cf_ad9250_ebz.bit** file.
 ==== Board Modifications ====
@@ Line 51: / Line 60: @@
 Please do the following modifications on the AD9250 evaluation board.
-  * Remove R609.
+  * Remove R609
-  * Remove R610.
+  * Remove R610
-  * Remove R604.
+  * Remove R604
-  * Remove R601.
+  * Remove R601
+  * **Remove R551***
+  * **Remove R552***
+  * **Populate R549***
+  * **Populate R550***
+* The reference design uses REFCLK2 as the reference clock source. If the board defaults to REFCLK1, follow these instructions to switch to REFCLK2.
 ==== Running Demo (SDK) Program ====
 To begin make the following connections (see image below):
+<WRAP round 80% tip>
+\\
+For proper operation, it is important that the steps must be done in this exact order
-  * Connect the AD9250-EBZ board to the FMC Interposer board.
+</WRAP>
-  * Connect the interposer board to the **FMC-HPC** connector of KC705 board.
+  - Connect the AD9250-EBZ board to the FMC Interposer board.
-  * Connect power to KC705 and the AD9250-EBZ boards.
+  - Connect the interposer board to the **FMC-HPC** connector of KC705/(**FMC1-HPC** if VC707)/ZC706 board.
-  * Connect two USB cables from the PC to the //JTAG// and //UART// USB connectors on KC705.
+  - Connect power to KC705/VC707/ZC706 and the AD9250-EBZ boards. Make sure both are turned on.
-  * Connect an external clock source 250MHz (5dBm) to AD9250-EBZ board's J505 SMA connector.
+  - Connect two USB cables from the PC to the //JTAG// and //UART// USB connectors on KC705/VC707/ZC706. Do not run/load any software yet.
-  * Connect signal generators to the AIN-A/AIN-B, J301/J303 SMA connectors.
+  - Connect an external clock source 250MHz (5dBm) to AD9250-EBZ board's J505 SMA connector. Make sure this is active/on.
+  - Connect signal generators to the AIN-A and/or AIN-B, J301/J303 SMA connectors.
+  - Load the FPGA image/SDK with your favorite Xilinx Tool.
-The quick start bit file configures the AD9250 for all test modes and verifies the captured data accordingly. After the hardware setup, turn the power on to the KC705 and the AD9250-EBZ boards.
+The quick start bit file configures the AD9250 for all test modes and verifies the captured data accordingly. After the hardware setup, turn the power on to the KC705/VC707/ZC706 and the AD9250-EBZ boards.
-{{:resources:fpga:xilinx:interposer:cf_ad9250_ebz_setup.jpg?200|Hardware setup}}
+{{:resources:fpga:xilinx:fmc:ad9250_ebz:cf_ad9250_ebz_setup.jpg?200|Hardware setup}}
-Start IMPACT, and initialze the JTAG chain. The program should recognize the Kintex 7 device. Start a UART terminal (set to 57600 baud rate) and then program the device. If programming was successful, you should be seeing messages appear on the terminal as shown in figure below. After programming the AD9250, the program checks data capture on various test modes.
+Run the **//download.bat//** script located in the "//SDK/SDK_Workspace/bin//" folder provided within the HDL Reference Design. This script uses XMD to program the FPGA with the HDL Reference Design and download the Software Reference Design into the DDR.
-{{:resources:fpga:xilinx:interposer:cf_ad9250_ebz_uart.jpg?200|Terminal}}
+**Note:** The //download.bat// script assumes that the //Xilinx ISE Design Suite 14.4// is installed at this path:  //C:/Xilinx/14.4//. If the installation path on your computer is different please modify the script accordingly.
-After patterns and prbs sequences are verified, if no errors are present, you may use the chipscope busplot to see the captured signal (see below). The ADC data is available on pins [15:0] and [31:16] of UNIT:1 of chipscope.
+If programming was successful, you should be seeing messages appear on the terminal as shown in figure below. After programming the AD9250, the program checks data capture on various test modes.
-{{:resources:fpga:xilinx:interposer:cf_ad9250_ebz_chipscope.jpg?200|Chipscope Busplot}}
+{{:resources:fpga:xilinx:fmc:ad9250_ebz:ad9250_test.jpg?200|Terminal}}
-===== Using the reference design =====
+After the ADC test patterns and PRBS sequences are verified, if no errors are present, the reference design continuously reads data from the ADC. The ADC data can be viewed using the Chipscope project located in the "//Chipscope//" folder provided in the HDL Reference Design. These are the steps than need to be followed to view the ADC data in Chipscope:
+  * open Chipscope and press the **//Open Cable/Search JTAG Chain//** button (the leftmost button located under the File menu)
+  * open the //Chipscope/AD9250.cpj// project
+  * start the data capture
+This is how the output of the ADC looks like.
+{{:resources:fpga:xilinx:fmc:ad9250_ebz:cf_ad9250_ebz_chipscope.jpg?200|Chipscope Busplot}}
+===== Using the HDL reference design =====
+==== Functional description ====
 The reference design is built on a microblaze based system parameterized for linux. A functional block diagram of the design is given below.
-{{:resources:fpga:xilinx:interposer:cf_ad9250_bd.jpg?400|block diagram}}
+{{:resources:fpga:xilinx:fmc:ad9250_ebz:cf_ad9250_bd.jpg?400|block diagram}}
-The reference design consists of two pcores. The JESD core consists of the GTX units and the Xilinx JESD 204 IP core. The AD9250 core consists of three functional modules, the ADC interface, a PN9/PN23 monitor and a DMA interface.
+The reference design consists of two pcores. The JESD204B core consists of the GTX units and the Xilinx JESD204B IP core. The AD9250 core consists of three functional modules, the ADC interface, a PN9/PN23 monitor and a DMA interface.
-The ADC interface captures and buffers data from the JESD core. The DMA interface then transfers the samples to the external DDR-DRAM. The capture is initiated by the software. The status of capture (overflow, over the range) are reported back to the software.
+The ADC interface captures and buffers data from the JESD204B core. The DMA interface then transfers the samples to the external DDR-DRAM. The capture is initiated by the software. The status of capture (overflow, overrange) are reported back to the software.
+The JESD204B core and AD9250 core has an AXI lite interface that allows control and monitoring of the capture process.
+The reference design also includes the HDMI cores to run GTX eye scan.
-The JESD core and AD9250 core has an AXI lite interface that allows control and monitoring of the capture process.
 ==== Registers ====
-Please refer to the regmap.txt file in the pcores directory.
+Please refer to the //**regmap.txt**// file in the pcores directory.
 ==== Good To Know ====
@@ Line 100: / Line 133: @@
 The PN9/PN23 sequences are not compatible with O.150. Please use the equations given in the reference design.
+===== Using the Software Reference Design =====
+The Software Reference Design contains an example on how to:
+  * Initialize the AD9250 evaluation board
+  * Initialize the JESD204B HDL core
+  * Test the ADC communication using the test patterns and PRBS sequences generated by the AD9250
+  * Capture data from the AD9250 using DMA transfers
+The software project contains 2 components: the AD9250-EBZ reference design files and the AD9250 driver. All the components have to be downloaded from the links provided in the **Downloads** section.
+==== AD9250 Software Driver ====
+Below is presented a short description of all the functions provided in the driver.
+|< 100% 40% 60% >|
+^  Function  ^  Description  ^
+| int32_t **//ad9250_setup//**(int32_t spiBaseAddr, int32_t ssNo) | Configures the device. Receives as parameters the SPI peripheral AXI base address and the slave select line on which the slave is connected. Returns negative error code or 0 in case of success. |
+| int32_t **//ad9250_read//**(int32_t registerAddress) | Reads data from a register. Receives as parameter the address of the register to be read and returns the read data or negative error code. |
+| int32_t **//ad9250_write//**(int32_t registerAddress, int32_t registerValue) | Writes data into a register. Receives as parameters the address of the register to be written and the value to be written into the register. Returns 0 in case of success or negative error code. |
+| int32_t **//ad9250_transfer//**(void) | Initiates a transfer and waits for the operation to end. Returns the negative error code or 0 in case of success. |
+| int32_t **//ad9250_soft_reset//**(void) | Resets all registers to their default values. Returns negative error code or 0 in case of success. |
+| int32_t **//ad9250_chip_pwr_mode//**(int32_t mode) | Configures the power mode of the chip. Receives as parameter the power mode(0 - normal operation, 1 - power-down, 2 - standby). Negative error code or the set power mode. |
+| int32_t **//ad9250_select_channel_for_config//**(int32_t channel) | Selects a channel as the current channel for further configurations. Receives as parameter the channel index(1 - channel A, 2 - channel B, 3 - channel A and B). Returns negative error code or the selected channel. |
+| int32_t **//ad9250_test_mode//**(int32_t mode) | Sets the ADC's test mode. Receives as parameter the test mode{0, 1, 2, 3, 4, 5, 6, 7, 8, 15}. Returns the set test mode or negative error code. |
+| int32_t **//ad9250_offset_adj//**(int32_t adj) | Sets the offset adjustment. Receives as parameter the offset adjust value in LSBs from +31 to -32. Returns negative error code or the set offset adjustment. |
+| int32_t **//ad9250_output_disable//**(int32_t en) | Disables (1) or enables (0) the data output. Returns the negative error code or the output disable state. |
+| int32_t **//ad9250_output_invert//**(int32_t invert) | Activates the inverted (1) or normal (0) output mode. Returns the negative error code or the set output mode.  |
+| int32_t **//ad9250_output_format//**(int32_t format) | Specifies the output format. Receives as parameter the output format and returns the negative error code or the set output format. |
+| int32_t **//ad9250_reset_PN9//**(int32_t rst) | Sets (1) or clears (0) the reset short PN sequence bit(PN9). Returns the negative error code or the set PN9 status.  |
+| int32_t **//ad9250_reset_PN23//**(int32_t rst) | Sets (1) or clears (0) the reset long PN sequence bit(PN23). Returns the negative error code or the set PN23 status. |
+| int32_t **//ad9250_set_user_pattern//**(int32_t patternNo, int32_t user_pattern) | Configures a User Test Pattern. Receives as parameters the patterns to be configured, range 1..4 and the user's pattern. Returns negative error code or the selected user pattern. |
+| int32_t **//ad9250_bist_enable//**(int32_t enable) | Enables(1) or disables(0) the Build-In-Self-Test. Returns negative error code or the state of the enable bit. |
+| int32_t **//ad9250_bist_reset//**(int32_t reset) | Resets the Build-In-Self-Test. Receives as parameters the reset option. Negative error code or the state of the reset bit. |
+| int32_t **//ad9250_jesd204b_setup//**(void) | Configures the JESD204B interface. Returns negative error code or 0 in case of success. |
+| int32_t **//ad9250_jesd204b_pwr_mode//**(int32_t mode) | Configures the power mode of the JESD204B data transmit block. Receives as parameter the power mode(0 - normal operation, 1 - power-down, 2 - standby) Returns negative error code or the set power mode. |
+| int32_t **//ad9250_jesd204b_select_test_injection_point//**(int32_t injPoint) | Selects the point in the processing path of a lane, where the test data will be inserted. Receives as parameter the point in the processing path(1 - 8B/10B Encoder output, 2 - scramble input). Returns negative error code or the status of the data injection point bit. |
+| int32_t **//ad9250_jesd204b_test_mode//**(int32_t testMode) | Selects a JESD204B test mode. Receives as parameter the test mode{0, 1, 2, 3, 4, 5, 6, 8, 12, 13}. Returns the set test mode or negative error code. |
+| int32_t **//ad9250_jesd204b_invert_logic//**(int32_t invert) | Inverts the logic of JESD204B bits. Receives as parameter the invert option(1 - invert, 0 - non-invert). Returns negative error code or the set mode. |
+| int32_t **//ad9250_fast_detect_setup//**(void) | Configures the Fast-Detect module. Returns negative error code or 0 in case of success. |
+| int32_t **//ad9250_dcc_enable//**(int32_t enable) | Enables DC correction for use in the output data signal path. Receives as parameter the enable option (0 - correction off, 1 - correction on). Returns negative error code or the status of the enable bit. |
+| int32_t **//ad9250_dcc_bandwidth//**(int32_t bw)| Selects the bandwidth value for the DC correction circuit. Receives as parameter the DC correction bandwidth, range 0..13. Returns negative error code or the state of the bandwidth bits. |
+| int32_t **//ad9250_dcc_freeze//**(int32_t freeze) | Freezes DC correction value. Receives as parameter the freeze option(0 or 1). Returns negative error code or the status of the freeze bit. |
+==== Software Setup ====
+The **HDL Reference Design** for each supported Xilinx FPGA board contains a folder called //**SDK_Workspace**// which stores the Xilinx SDK project files needed to build the no-OS software and also the .bit files with the HDL design that must be programmed into the FPGA.
+These are the steps that need to be followed to recreate the software project:
+  * Copy the //**SDK_Workspace**// folder on your PC. Make sure that the path where it is stored does not contain any spaces.
+  * Copy the no-OS drivers source code to the //**SDK_Workspace/sw/src**// folder.
+{{:resources:fpga:xilinx:fmc:ad9250_ebz:src_files.png?200|no-OS driver Source Files}}
+  * Open the Xilinx SDK. When the SDK starts it asks you to provide a folder where to store the workspace. Any folder can be provided.
+  * In the SDK select the //**File->Import**// menu option to import the software projects into the workspace.
+{{:resources:fpga:xilinx:fmc:ad9250_ebz:file_import.png?200|Import Projects}}
+  * In the //Import// window select the //**General->Existing Projects into Workspace**// option.
+{{:resources:fpga:xilinx:fmc:ad9250_ebz:existing_project_import.png?200|Existing Projects Import}}
+  * In the //Import Projects// window select the //**SDK_Workspace**// folder as root directory. After the root directory is chosen the projects that reside in that directory will appear in the //Projects// list. Press //Finish// to finalize the import process.
+{{:resources:fpga:xilinx:fmc:ad9250_ebz:projects_import.png?200|Projects Import}}
+  * The //Project Explorer// window now shows the projects that exist in the workspace and the files for each project. The SDK should automatically build the projects and the //Console// window will display the result of the build. If the build is not done automatically select the //**Project->Build Automatically**// menu option.
+{{:resources:fpga:xilinx:fmc:ad9250_ebz:project_explorer.png?200|Project Explorer}}
+  * At this point the software project setup is complete, the FPGA can be programmed and the software can be downloaded into the system.
+The example code is located in the ”//main.c//” file and the implementations of the test routines can be found in the "//cf_ad9250.c//" file.
 ===== Downloads =====
-FPGA Referece Designs:
+The HDL Reference Designs and the no-OS Software can be downloaded from the Analog Devices github.\\
+\\
+<WRAP round important 80%>
+Only Xilinx coregen xco files are provided with the HDL Reference Design. You must regenerate the IP core files using this file. See [[/resources/eval/user-guides/ad-fmcomms1-ebz/reference_hdl|generating Xilinx netlist/verilog files from xco files]] for details.\\
+\\
+The software project contains 2 components: the AD9250-EBZ reference design files and the AD9250 driver. All the components have to be downloaded from the links below.
+</WRAP>
+**HDL Reference Designs:**
 <WRAP round download 80%>
-  * {{:resources:fpga:xilinx:interposer:cf_ad9250_ebz_edk_14_1_2012_11_28.tar.gz| KC705 }}
+  * **KC705 ** {{:resources:fpga:xilinx:interposer:cf_ad9250_ebz_edk_14_4_2013_04_04.tar.gz}}
+  * **VC707 ** {{:resources:fpga:xilinx:interposer:cf_ad9250_ebz_vc707_edk_14_4_2013_04_04.tar.gz}}
+  * **ZC706 ** {{:resources:fpga:xilinx:interposer:cf_ad9250_ebz_zc706_edk_14_4_2013_04_04.tar.gz}}
 </WRAP>
-Only Xilinx coregen xco files are provided with the reference design. You must regenerate the IP core files using this file. For help and support, please use [[ez>community/fpga|Engineer Zone]].
+**no-OS Software:**
+<WRAP round download 80%>
+\\
+  * **AD9250 Driver:                   ** https://github.com/analogdevicesinc/no-OS/tree/master/drivers/adc/ad9250
+  * **AD9250-EBZ Reference Design:     ** https://github.com/analogdevicesinc/no-OS/tree/master/AD9250-EBZ
+\\
+</WRAP>
+**Board Files:**
+<WRAP round download 80%>
+\\
+  * {{:resources:fpga:xilinx:fmc:ad9250_ebz:ad9250_schematic_02_12008.pdf|Rev C Schematics for the card}}
+  * {{:resources:fpga:xilinx:fmc:ad9250_ebz:ad9250_gerber_20_012008b.zip|AD9250-250EBZ Gerber/Layout Fabrication Files}}
+\\
+</WRAP>
-===== Tar file contents =====
+<WRAP round help 80%>
+\\
-The tar file contains, in most cases, the following files and/or directories. To rebuild the reference design simply double click the XMP file and run the tool. To build SDK, select a workspace and use the C file to build the elf file. Please refer to [[http://www.xilinx.com/support/documentation/dt_edk_edk13-2.htm|Xilinx EDK documentation]] for details.
+  * Questions? [[ez> | Ask Help & Support]].
+\\
+</WRAP>
+==== Reference Design Contents ====
+^ HDL Reference Design   ^^
 | license.txt | ADI license & copyright information. |
 | system.mhs  | MHS file. |
@@ Line 121: / Line 243: @@
 | sw/         | Software (Xilinx SDK) & bit file(s). |
 | cf_lib/edk/pcores/     | Reference design core file(s) (Xilinx EDK). |
+^ Software Reference Design   ^^
+| cf_ad9250.h | Header file containing the registers definitions for the AD9250 HDL core. |
+| cf_ad9250.c | Implementation of the AD9250 HDL core access functions and ADC test and capture functions. |
+| spi.h | Header file for the Xilinx AXI SPI driver. |
+| spi.c | Implementation file for the Xilinx AXI SPI driver. |
+| main.c | Implementation of the program's main function. |
+^ AD9250 Software Driver   ^^
+| AD9250.h | AD9250 software driver header file. |
+| AD9250_cfg.h | AD9250 software driver configuration file. |
+| AD9250.c | AD9250 software driver implementation file. |
 ===== More information =====
+<WRAP round help 80%>
-  * [[http://www.vita.com/fmc.html|VITA's FMC info]]
+\\
+  * [[http://www.vita.com/fmc|VITA's FMC info]]
   * [[ez>community/fpga|Ask questions about the FPGA reference design]]
+\\
+</WRAP>

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