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resources:fpga:xilinx:interposer:ad9116 [28 Feb 2012 11:26] – [Downloads] Andrei Cozma | resources:fpga:xilinx:interposer:ad9116 [31 Jan 2024 09:53] (current) – Mark as obsolete iulia Moldovan | ||
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- | ====== AD971x/ | + | ====== |
+ | |||
+ | <WRAP round important 65%> | ||
+ | Support for AD971x/ | ||
+ | </ | ||
===== Supported Devices ===== | ===== Supported Devices ===== | ||
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===== Evaluation Boards ===== | ===== Evaluation Boards ===== | ||
- | * [[adi>en/ | + | * [[adi> |
- | * [[adi>en/ | + | * [[adi> |
- | * [[adi>en/ | + | * [[adi> |
- | * [[adi>en/ | + | * [[adi> |
===== Introduction ===== | ===== Introduction ===== | ||
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The flexible power supply operating range of 1.8 V to 3.3 V and low power dissipation of the AD9114/ | The flexible power supply operating range of 1.8 V to 3.3 V and low power dissipation of the AD9114/ | ||
- | **HW Platform(s): | + | **HW Platform(s): |
**System:** Microblaze, AXI, UART | **System:** Microblaze, AXI, UART | ||
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==== Running Demo (SDK) Program ==== | ==== Running Demo (SDK) Program ==== | ||
- | <note tip>If you are not familiar with ML605 and/or Xilix tools, please visit\\ [[http://www.xilinx.com/products/ | + | <WRAP tip>If you are not familiar with ML605 and/or Xilix tools, please visit\\ [[xilinx>products/ |
- | </note> | + | </WRAP> |
Extract the project from the archive file (AD911x.zip) to the location you desire. | Extract the project from the archive file (AD911x.zip) to the location you desire. | ||
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- **Section 13** User must press the button in order for the AD9512 related modifications to take place | - **Section 13** User must press the button in order for the AD9512 related modifications to take place | ||
- | <note important> | + | <WRAP important> |
* If you drag a slider and it doesn' | * If you drag a slider and it doesn' | ||
* If you receive (Pc Port Open) at the bottom of the screen, please press Stop, close your COM port, reprogram the FPGA, launch the software and try again. | * If you receive (Pc Port Open) at the bottom of the screen, please press Stop, close your COM port, reprogram the FPGA, launch the software and try again. | ||
* In **Section 10** please select DIVSEL so that (DCLKIO / 2^n) is between 0.5 MHz and 4 MHz for optimal Calibration results | * In **Section 10** please select DIVSEL so that (DCLKIO / 2^n) is between 0.5 MHz and 4 MHz for optimal Calibration results | ||
- | </note> | + | </WRAP> |
===== Downloads ===== | ===== Downloads ===== | ||
+ | |||
+ | <WRAP round download 80%> | ||
{{: | {{: | ||
+ | </ | ||
+ | |||
+ | ===== Support ===== | ||
+ | |||
+ | ==== HDL / Hardware Questions ==== | ||
+ | |||
+ | For questions regarding the AD9116 chip, or the AD911x eval board, please ask them in the [[ez> | ||
+ | |||
+ | ==== No-OS Questions ==== | ||
+ | For questions regarding the no-OS drivers for any of the components on the AD-FMCOMMS2-EBZ please use the [[ez> | ||