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====== AD7091 FMC-SDP Interposer & Evaluation Board / Xilinx AC701 Reference Design ======


===== Supported Devices =====

  * [[adi>AD7091]]

===== Evaluation Boards =====

  * [[adi>EVAL-AD7091SDZ]]

====== Overview ======

This document presents the steps to setup an environment for using the **[[adi>AD7091|EVAL-AD7091SDZ]]** evaluation board together with the Xilinx AC701 FPGA board and the Xilinx Embedded Development Kit (EDK). Below is presented a picture of the EVAL-AD7091SDZ Evaluation Board with the Xilinx AC701 board.

{{ :resources:fpga:xilinx:interposer:ad7091_ac701.jpg?400 }}

{{page>resources:fpga:xilinx:interposer:common_sdp}}

Below is presented a picture of **SDP-B** Controller Board with the **EVAL-AD7091SDZ** Evaluation Board.

{{ :resources:fpga:xilinx:interposer:ad7091_sdp1z.jpg?400 }}

The [[adi>AD7091]] is a 12-bit successive approximation register analog-to-digital converter (SAR ADC) that offers ultralow power consumption (typically 367 µA at 3 V and 1 MSPS) while achieving fast throughput rates (1 MSPS with a 50 MHz SCLK). The AD7091 operates from a single 2.09 V to 5.25 V power supply. The AD7091 also features an on-chip conversion clock and a high speed serial interface.

The **EVAL-AD7091SDZ** evaluation board is a member of a growing number of boards available for the **SDP**.  It was designed to help customers evaluate performance or quickly prototype new **AD7091** circuits and reduce design time.

===== More information =====
  * [[adi>AD7091|AD7091 Product Info]] - pricing, samples, datasheet
  * [[adi>static/imported-files/user_guides/UG-447.pdf | EVAL-AD7091SDZ evaluation board user guide]]
  * [[xilinx>products/boards-and-kits/EK-A7-AC701-G.htm | Xilinx AC701 FPGA board]]

====== Getting Started ======

The first objective is to ensure that you have all of the items needed and to install the software tools so that you are ready to create and run the evaluation project.

===== Required Hardware =====

  * [[xilinx>products/boards-and-kits/EK-A7-AC701-G.htm | Xilinx AC701 FPGA board]]
  * FMC-SDP adapter board
  * **EVAL-AD7091SDZ** evaluation board

===== Required Software =====

  * Xilinx ISE 14.6
  * A UART terminal (Tera Term/Hyperterminal/Termite), baud rate 115200.

===== Downloads =====
<WRAP round download 80%>
\\
  * **IP Core Files:** https://github.com/analogdevicesinc/fpgahdl_xilinx/tree/master/cf_lib/edk/pcores/axi_ad7091_v1_00_a
  * **EDK AC701 Reference project:** https://github.com/analogdevicesinc/fpgahdl_xilinx/tree/master/cf_sdp_adc/cf_ad7091_ac701
  * **AD7091 Drivers:** https://github.com/analogdevicesinc/no-OS/tree/master/drivers/adc/ad7091r
  * **ADC specific files:** https://github.com/analogdevicesinc/no-OS/tree/master/legacy/platform_drivers/Xilinx/SDP_ADC/AD7091
  * **Platform specific files:** https://github.com/analogdevicesinc/no-OS/tree/master/legacy/platform_drivers/Xilinx/SDP_Common
\\
</WRAP>

====== Run the Demonstration Project ======

===== Hardware Setup =====

<WRAP important>Before connecting the ADI evaluation board to the Xilinx AC701 make sure that the VADJ_FPGA voltage of the AC701 is set to 3.3V. For more details on how to change the setting for VADJ_FPGA visit the Xilinx AC701 product page.</WRAP>

  * Use the FMC-SDP interposer to connect the ADI evaluation board to the Xilinx AC701 board on the FMC LPC connector.
  * Connect the JTAG and UART cables to the AC701 and power up the FPGA board.
  * Power up the the EVAL-AD7091SDZ with 7 V to 9 V external power supply.

The next step is to setup the software project. 

===== Software Project Setup =====

The next steps should be followed to recreate the software project of the reference design:

  * First clone the AC701 Reference project for AD7091 and the ADI IP cores from Github to your computer, by using the following link: https://github.com/analogdevicesinc/fpgahdl_xilinx/ 

  * Copy the folder **../fpgahdl_xilinx/cf_lib** and **../fpgahdl_xilinx/cf_sdp_adc/cf_ad7091_ac701** to your working directory
  * Open a Xilinx SDK and setup your workspace to **%Working directory%/cf_ad7091_ac701/SDK/SDK_Workspace**
  * In the SDK select the **File->Import** menu option to import the software project into your workspace.
{{:resources:fpga:xilinx:fmc:ad9739a_ebz:file_import.png?200|Import Projects}}
  * In the //Import// window select the **General->Existing Projects into Workspace** option.
{{:resources:fpga:xilinx:fmc:ad9739a_ebz:existing_project_import.png?200|Existing Projects Import}}
  * In the //Import Projects// window select the **%Working directory%/cf_ad7091_ac701/** folder as root directory and verify if all the three project (**hw**, **bsp**, **sw**) are checked.
{{:resources:fpga:xilinx:interposer:import_project_adc.png?200|Selecting Existing Projects}}
  * The Project Explorer window now shows the projects that exist in the workspace without software files.
{{:resources:fpga:xilinx:fmc:ad9739a_ebz:project_explorer.jpg?200|Project Explorer}}
  * Now you have to add the source files to your project. You can download all the source files for the current reference project using the links from the **Downloads** section. List of source files for the current project is:  
                       * **Driver files** : //ad7091.h// and //ad7091.c//
                       * **Platform specific files** : //Communication.h//, //Communication.c//, //TIME.h// and //TIME.c// 
                       * **ADC specific files** : //main.c// and //xdma_config.h//
  * All these files must be copied into the **%Working directory%/cf_ad7091_ac701/SDK/SDK_Workspace/sw/src/** folder.
  * The SDK should automatically build the project and the Console window will display the result of the build. If the build is not done automatically, select the Project→Build Automatically menu option.
  * If the project was built without any errors, you need to download the data capture script, from [[https://github.com/analogdevicesinc/no-OS/tree/master/legacy/platform_drivers/Xilinx/SDP_ADC/AD7091|here]]. Copy the **Data_capture** folder to your working directory.  
  * Run the **data_capture.bat** script. If the acquisition is finished with success, it should appear a file called **Acquisition.csv** with the result of the conversion.
{{:resources:fpga:xilinx:interposer:acquisition_finished.png?600|Acquisition Finished}}
  * By default the length of a transaction is 16k samples. The input signal used in this reference design was a 10 Khz sine wave.
{{:resources:fpga:xilinx:interposer:acquisition_result.png?600|Acquisition Result}}

====== More information ======
{{page>/resources/fpga/xilinx/interposer/ez_common}}
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