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resources:fpga:xilinx:interposer:ad6673 [22 Jul 2019 10:04] – Update no-OS driver link Andrei Drimbarean | resources:fpga:xilinx:interposer:ad6673 [25 Jan 2021 19:33] (current) – update renesas links after their web site update Robin Getz | ||
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===== Supported Devices ===== | ===== Supported Devices ===== | ||
- | * [[http:// | + | * [[adi>EVAL-AD6673|AD6673 Evaluation Board]] |
- | * [[http:// | + | * [[adi>EVAL-ADC-FMC-INT|ADC FMC Interposer Board]] |
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<WRAP round important 80%> | <WRAP round important 80%> | ||
- | Only Xilinx coregen xco files are provided with the HDL Reference Design. You must regenerate the IP core files using this file. See [[http:// | + | Only Xilinx coregen xco files are provided with the HDL Reference Design. You must regenerate the IP core files using this file. See [[/ |
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The software project contains 2 components: the AD6673-EBZ reference design files and the AD6673 driver. All the components have to be downloaded from the links below. | The software project contains 2 components: the AD6673-EBZ reference design files and the AD6673 driver. All the components have to be downloaded from the links below. | ||
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<WRAP round help 80%> | <WRAP round help 80%> | ||
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- | * Questions? [[http://ez.analog.com/ | + | * Questions? [[ez>fpga|Ask Help & Support]]. |
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