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resources:fpga:xilinx:interposer:ad6673 [25 Feb 2013 09:51] – The page was reorganized. Dan Nechita | resources:fpga:xilinx:interposer:ad6673 [25 Jan 2021 19:33] (current) – update renesas links after their web site update Robin Getz | ||
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===== Introduction ===== | ===== Introduction ===== | ||
- | The [[ADI> | + | The [[ADI> |
===== Supported Devices ===== | ===== Supported Devices ===== | ||
- | * [[http:// | + | * [[adi>EVAL-AD6673|AD6673 Evaluation Board]] |
- | * [[http:// | + | * [[adi>EVAL-ADC-FMC-INT|ADC FMC Interposer Board]] |
{{: | {{: | ||
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===== Supported Carriers ===== | ===== Supported Carriers ===== | ||
- | * [[xilinx> | + | * [[xilinx> |
- | * [[xilinx> | + | * [[xilinx> |
- | * [[xilinx> | + | * [[xilinx> |
===== Quick Start Guide ===== | ===== Quick Start Guide ===== | ||
- | The reference design zip file contains a bit file combined with a SDK elf file for a quick demonstration of the programming and data capture. | + | The reference design zip file contains a bit file and a SDK elf file for a quick demonstration of the programming and data capture. |
==== Required Hardware ==== | ==== Required Hardware ==== | ||
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* Xilinx ISE Design Suite 14.4 | * Xilinx ISE Design Suite 14.4 | ||
- | * A UART terminal (Tera Term/ | + | * A UART terminal (Tera Term/ |
==== Board Modifications ==== | ==== Board Modifications ==== | ||
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To begin make the following connections (see image below): | To begin make the following connections (see image below): | ||
- | <WRAP tip>It is important for proper operation, the steps must be done in this exact order</ | + | <WRAP tip round 80%> |
+ | \\ | ||
+ | For proper operation, | ||
+ | </ | ||
- Connect the AD6673-EBZ board to the FMC Interposer board. | - Connect the AD6673-EBZ board to the FMC Interposer board. | ||
- Connect the interposer board to the **FMC-HPC** connector of KC705/ | - Connect the interposer board to the **FMC-HPC** connector of KC705/ | ||
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- Connect two USB cables from the PC to the //JTAG// and //UART// USB connectors on KC705/ | - Connect two USB cables from the PC to the //JTAG// and //UART// USB connectors on KC705/ | ||
- Connect an external clock source 250MHz (5dBm) to AD6673-EBZ board' | - Connect an external clock source 250MHz (5dBm) to AD6673-EBZ board' | ||
- | - Connect signal generators to the AIN-A/ | + | - Connect signal generators to the AIN-A and/or AIN-B, J301/J303 SMA connectors. |
- Load the FPGA image/SDK with your favorite Xilinx Tool. | - Load the FPGA image/SDK with your favorite Xilinx Tool. | ||
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If programming was successful, you should be seeing messages appear on the terminal as shown in figure below. After programming the AD6673, the program checks data capture on various test modes. | If programming was successful, you should be seeing messages appear on the terminal as shown in figure below. After programming the AD6673, the program checks data capture on various test modes. | ||
- | {{: | + | {{: |
- | After the ADC test patterns | + | After the ADC test patterns are verified, if no errors are present, the reference design continuously reads data from the ADC. The ADC data can be viewed using the Chipscope project located in the "// |
* open Chipscope and press the **//Open Cable/ | * open Chipscope and press the **//Open Cable/ | ||
* open the // | * open the // | ||
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The reference design is built on a microblaze based system parameterized for linux. A functional block diagram of the design is given below. | The reference design is built on a microblaze based system parameterized for linux. A functional block diagram of the design is given below. | ||
- | {{: | ||
- | The reference design consists of two pcores. The JESD core consists of the GTX units and the Xilinx JESD 204 IP core. The AD6673 core consists of three functional modules, the ADC interface, a PN9/PN23 monitor and a DMA interface. | + | {{: |
- | The ADC interface captures and buffers data from the JESD core. The DMA interface then transfers the samples to the external DDR-DRAM. The capture is initiated by the software. The status of capture (overflow, over the range) are reported back to the software. | ||
- | The JESD core and AD6673 core has an AXI lite interface that allows control and monitoring of the capture process. | + | The reference design consists of two pcores. The JESD204B core consists of the GTX units and the Xilinx JESD204B IP core. The AD6673 core consists of three functional modules, the ADC interface, a PN9/PN23 monitor and a DMA interface. |
+ | |||
+ | The ADC interface captures and buffers data from the JESD204B core. The DMA interface then transfers the samples to the external DDR-DRAM. The capture is initiated by the software. The status of capture (overflow, over the range) are reported back to the software. | ||
+ | |||
+ | The JESD204B | ||
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The Software Reference Design contains an example on how to: | The Software Reference Design contains an example on how to: | ||
* Initialize the AD6673 evaluation board | * Initialize the AD6673 evaluation board | ||
- | * Initialize the JESD HDL core | + | * Initialize the JESD204B |
- | * Test the ADC communication using the test patterns | + | * Test the ADC communication using the test patterns generated by the AD6673 |
* Capture data from the AD6673 using DMA transfers | * Capture data from the AD6673 using DMA transfers | ||
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* Copy the no-OS drivers source code to the // | * Copy the no-OS drivers source code to the // | ||
{{: | {{: | ||
- | * Open the Xilinx SDK. When the SDK starts it asks for a to provide a folder where to store the workspace. Any folder can be provided. | + | * Open the Xilinx SDK. When the SDK starts it asks you to provide a folder where to store the workspace. Any folder can be provided. |
* In the SDK select the // | * In the SDK select the // | ||
{{: | {{: | ||
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* In the //Import Projects// window select the // | * In the //Import Projects// window select the // | ||
{{: | {{: | ||
- | * The //Project Explorer// window now shows the projects that exist in the workspace and the files for each project. The SDK should automatically build the projects and the //Console// window will display | + | * The //Project Explorer// window now shows the projects that exist in the workspace and the files for each project. The SDK should automatically build the projects and the //Console// window will display the result of the build. If the build is not done automatically select the // |
{{: | {{: | ||
* At this point the software project setup is complete, the FPGA can be programmed and the software can be downloaded into the system. | * At this point the software project setup is complete, the FPGA can be programmed and the software can be downloaded into the system. | ||
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\\ | \\ | ||
<WRAP round important 80%> | <WRAP round important 80%> | ||
- | Only Xilinx coregen xco files are provided with the HDL Reference Design. You must regenerate the IP core files using this file. See [[http:// | + | Only Xilinx coregen xco files are provided with the HDL Reference Design. You must regenerate the IP core files using this file. See [[/ |
\\ | \\ | ||
The software project contains 2 components: the AD6673-EBZ reference design files and the AD6673 driver. All the components have to be downloaded from the links below. | The software project contains 2 components: the AD6673-EBZ reference design files and the AD6673 driver. All the components have to be downloaded from the links below. | ||
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<WRAP round download 80%> | <WRAP round download 80%> | ||
\\ | \\ | ||
- | * **AD6673 Driver: | + | * **AD6673 Driver: |
* **AD6673-EBZ Reference Design: | * **AD6673-EBZ Reference Design: | ||
+ | \\ | ||
</ | </ | ||
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* {{: | * {{: | ||
* {{: | * {{: | ||
+ | \\ | ||
</ | </ | ||
<WRAP round help 80%> | <WRAP round help 80%> | ||
\\ | \\ | ||
- | * Questions? [[http://ez.analog.com/ | + | * Questions? [[ez>fpga|Ask Help & Support]]. |
+ | \\ | ||
</ | </ | ||
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<WRAP round help 80%> | <WRAP round help 80%> | ||
\\ | \\ | ||
- | + | | |
- | | + | |
* [[ez> | * [[ez> | ||
+ | \\ | ||
</ | </ | ||
- |