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| Both sides previous revisionPrevious revision | Next revisionBoth sides next revision | ||
| resources:fpga:xilinx:interposer:ad6673 [24 Apr 2013 11:38] – [Using the Software Reference Design] Lucian Sin | resources:fpga:xilinx:interposer:ad6673 [22 Feb 2017 19:42] – Canonical spelling of JESD204B Lars-Peter Clausen | ||
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| - | The reference design consists of two pcores. The JESD core consists of the GTX units and the Xilinx | + | The reference design consists of two pcores. The JESD204B |
| - | The ADC interface captures and buffers data from the JESD core. The DMA interface then transfers the samples to the external DDR-DRAM. The capture is initiated by the software. The status of capture (overflow, over the range) are reported back to the software. | + | The ADC interface captures and buffers data from the JESD204B |
| - | The JESD core and AD6673 core has an AXI lite interface that allows control and monitoring of the capture process. | + | The JESD204B |
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| The Software Reference Design contains an example on how to: | The Software Reference Design contains an example on how to: | ||
| * Initialize the AD6673 evaluation board | * Initialize the AD6673 evaluation board | ||
| - | * Initialize the JESD HDL core | + | * Initialize the JESD204B |
| * Test the ADC communication using the test patterns generated by the AD6673 | * Test the ADC communication using the test patterns generated by the AD6673 | ||
| * Capture data from the AD6673 using DMA transfers | * Capture data from the AD6673 using DMA transfers | ||
resources/fpga/xilinx/interposer/ad6673.txt · Last modified: 25 Jan 2021 19:33 by Robin Getz