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resources:fpga:xilinx:interposer:ad6673 [25 Feb 2013 09:51] – The page was reorganized. Dan Nechitaresources:fpga:xilinx:interposer:ad6673 [24 Apr 2013 11:38] – [Using the Software Reference Design] Lucian Sin
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 ===== Introduction ===== ===== Introduction =====
  
-The [[ADI>AD6673]] is an 11-bit, 250 MSPS, dual-channel intermediate frequency (IF) receiver specifically designed to support multi-antenna systems in telecommunication applications where high dynamic range performance, low power, and small size are desired. This reference design includes the device data capture via the JESD204B serial interface and the SPI interface. The samples are written to the external DDR-DRAM on the carrier. It allows programming the device and monitoring it's internal registers via SPI. +The [[ADI>AD6673]] is an 11-bit, 250 MSPS, dual-channel intermediate frequency (IF) receiver specifically designed to support multi-antenna systems in telecommunication applications where high dynamic range performance, low power, and small size are desired. This reference design includes the device data capture via the JESD204B serial interface and the SPI interface. The samples are written to the external DDR-DRAM on the carrier. It allows programming the device and monitoring its internal registers via SPI. 
  
 ===== Supported Devices ===== ===== Supported Devices =====
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 ===== Supported Carriers ===== ===== Supported Carriers =====
  
-  * [[xilinx> KC705]]  +  * [[xilinx>KC705]]  
-  * [[xilinx> VC707]]  +  * [[xilinx>VC707]]  
-  * [[xilinx> ZC706]] +  * [[xilinx>ZC706]] 
  
  
 ===== Quick Start Guide ===== ===== Quick Start Guide =====
  
-The reference design zip file contains a bit file combined with a SDK elf file for a quick demonstration of the programming and data capture. All you need is the hardware, Xilinx ISE Design Suite 14.4 and a PC running a UART terminal. +The reference design zip file contains a bit file and a SDK elf file for a quick demonstration of the programming and data capture. The reference design has been tested with KC705, VC707 and ZC706. The notes below refer to KC705, the procedure is same for the other boards. Please make sure you are using the correct reference design for the board(s) that you have.
  
 ==== Required Hardware ==== ==== Required Hardware ====
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   * Xilinx ISE Design Suite 14.4   * Xilinx ISE Design Suite 14.4
-  * A UART terminal (Tera Term/Hyperterminal), Baud rate 57600.+  * A UART terminal (Tera Term/Hyperterminal), Baud rate 57600(115200 for ZC706).
  
 ==== Board Modifications ==== ==== Board Modifications ====
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 To begin make the following connections (see image below): To begin make the following connections (see image below):
-<WRAP tip>It is important for proper operation, the steps must be done in this exact order</WRAP>+<WRAP tip round 80%> 
 +\\ 
 +For proper operation, it is important that the steps must be done in this exact order 
 +</WRAP>
   - Connect the AD6673-EBZ board to the FMC Interposer board.   - Connect the AD6673-EBZ board to the FMC Interposer board.
   - Connect the interposer board to the **FMC-HPC** connector of KC705/(**FMC1-HPC** if VC707)/ZC706 board.   - Connect the interposer board to the **FMC-HPC** connector of KC705/(**FMC1-HPC** if VC707)/ZC706 board.
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   - Connect two USB cables from the PC to the //JTAG// and //UART// USB connectors on KC705/VC707/ZC706. Do not run/load any software yet.   - Connect two USB cables from the PC to the //JTAG// and //UART// USB connectors on KC705/VC707/ZC706. Do not run/load any software yet.
   - Connect an external clock source 250MHz (5dBm) to AD6673-EBZ board's J505 SMA connector. Make sure this is active/on.   - Connect an external clock source 250MHz (5dBm) to AD6673-EBZ board's J505 SMA connector. Make sure this is active/on.
-  - Connect signal generators to the AIN-A/AIN-B, J301/J303 SMA connectors.+  - Connect signal generators to the AIN-A and/or AIN-B, J301/J303 SMA connectors.
   - Load the FPGA image/SDK with your favorite Xilinx Tool.   - Load the FPGA image/SDK with your favorite Xilinx Tool.
  
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 If programming was successful, you should be seeing messages appear on the terminal as shown in figure below. After programming the AD6673, the program checks data capture on various test modes.  If programming was successful, you should be seeing messages appear on the terminal as shown in figure below. After programming the AD6673, the program checks data capture on various test modes. 
  
-{{:resources:fpga:xilinx:fmc:ad6673_ebz:ad6673_test.png?200|Terminal}}+{{:resources:fpga:xilinx:fmc:ad6673_ebz:ad6673_test.jpg?200|Terminal}}
  
-After the ADC test patterns and PRBS sequences are verified, if no errors are present, the reference design continuously reads data from the ADC. The ADC data can be viewed using the Chipscope project located in the "//Chipscope//" folder provided in the HDL Reference Design. These are the steps than need to be followed to view the ADC data in Chipscope:+After the ADC test patterns are verified, if no errors are present, the reference design continuously reads data from the ADC. The ADC data can be viewed using the Chipscope project located in the "//Chipscope//" folder provided in the HDL Reference Design. These are the steps than need to be followed to view the ADC data in Chipscope:
   * open Chipscope and press the **//Open Cable/Search JTAG Chain//** button (the leftmost button located under the File menu)   * open Chipscope and press the **//Open Cable/Search JTAG Chain//** button (the leftmost button located under the File menu)
   * open the //Chipscope/AD6673.cpj// project    * open the //Chipscope/AD6673.cpj// project 
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 The reference design is built on a microblaze based system parameterized for linux. A functional block diagram of the design is given below. The reference design is built on a microblaze based system parameterized for linux. A functional block diagram of the design is given below.
  
-{{:resources:fpga:xilinx:fmc:ad6673_ebz:cf_ad6673_bd.jpg?400|block diagram}}+ 
 +{{:resources:fpga:xilinx:fmc:ad6673_ebz:cf_ad6673_bd.jpg?500|block diagram}} 
  
 The reference design consists of two pcores. The JESD core consists of the GTX units and the Xilinx JESD 204 IP core. The AD6673 core consists of three functional modules, the ADC interface, a PN9/PN23 monitor and a DMA interface.  The reference design consists of two pcores. The JESD core consists of the GTX units and the Xilinx JESD 204 IP core. The AD6673 core consists of three functional modules, the ADC interface, a PN9/PN23 monitor and a DMA interface. 
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   * Initialize the AD6673 evaluation board   * Initialize the AD6673 evaluation board
   * Initialize the JESD HDL core   * Initialize the JESD HDL core
-  * Test the ADC communication using the test patterns and PRBS sequences generated by the AD6673+  * Test the ADC communication using the test patterns generated by the AD6673
   * Capture data from the AD6673 using DMA transfers   * Capture data from the AD6673 using DMA transfers
  
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   * Copy the no-OS drivers source code to the //**SDK_Workspace/sw/src**// folder.   * Copy the no-OS drivers source code to the //**SDK_Workspace/sw/src**// folder.
 {{:resources:fpga:xilinx:fmc:ad6673_ebz:src_files.png?200|no-OS driver Source Files}} {{:resources:fpga:xilinx:fmc:ad6673_ebz:src_files.png?200|no-OS driver Source Files}}
-  * Open the Xilinx SDK. When the SDK starts it asks for a to provide a folder where to store the workspace. Any folder can be provided.+  * Open the Xilinx SDK. When the SDK starts it asks you to provide a folder where to store the workspace. Any folder can be provided.
   * In the SDK select the //**File->Import**// menu option to import the software projects into the workspace.   * In the SDK select the //**File->Import**// menu option to import the software projects into the workspace.
 {{:resources:fpga:xilinx:fmc:ad6673_ebz:file_import.png?200|Import Projects}} {{:resources:fpga:xilinx:fmc:ad6673_ebz:file_import.png?200|Import Projects}}
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   * In the //Import Projects// window select the //**SDK_Workspace**// folder as root directory. After the root directory is chosen the projects that reside in that directory will appear in the //Projects// list. Press //Finish// to finalize the import process.   * In the //Import Projects// window select the //**SDK_Workspace**// folder as root directory. After the root directory is chosen the projects that reside in that directory will appear in the //Projects// list. Press //Finish// to finalize the import process.
 {{:resources:fpga:xilinx:fmc:ad6673_ebz:projects_import.png?200|Projects Import}}  {{:resources:fpga:xilinx:fmc:ad6673_ebz:projects_import.png?200|Projects Import}} 
-  * The //Project Explorer// window now shows the projects that exist in the workspace and the files for each project. The SDK should automatically build the projects and the //Console// window will display the the result of the build. If the build is not done automatically select the //**Project->Build Automatically**// menu option.+  * The //Project Explorer// window now shows the projects that exist in the workspace and the files for each project. The SDK should automatically build the projects and the //Console// window will display the result of the build. If the build is not done automatically select the //**Project->Build Automatically**// menu option.
 {{:resources:fpga:xilinx:fmc:ad6673_ebz:project_explorer.png?200|Project Explorer}} {{:resources:fpga:xilinx:fmc:ad6673_ebz:project_explorer.png?200|Project Explorer}}
   * At this point the software project setup is complete, the FPGA can be programmed and the software can be downloaded into the system.   * At this point the software project setup is complete, the FPGA can be programmed and the software can be downloaded into the system.
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   * **AD6673 Driver:                   ** https://github.com/analogdevicesinc/no-OS/tree/master/drivers/AD6673   * **AD6673 Driver:                   ** https://github.com/analogdevicesinc/no-OS/tree/master/drivers/AD6673
   * **AD6673-EBZ Reference Design:     ** https://github.com/analogdevicesinc/no-OS/tree/master/AD6673-EBZ    * **AD6673-EBZ Reference Design:     ** https://github.com/analogdevicesinc/no-OS/tree/master/AD6673-EBZ 
 +\\
 </WRAP> </WRAP>
  
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   * {{:resources:fpga:xilinx:fmc:ad6673_ebz:ad6673_schematic_02_12008.pdf|Rev C Schematics for the card}}   * {{:resources:fpga:xilinx:fmc:ad6673_ebz:ad6673_schematic_02_12008.pdf|Rev C Schematics for the card}}
   * {{:resources:fpga:xilinx:fmc:ad6673_ebz:ad6673_gerber_20_012008b.zip|AD6673-250EBZ Gerber/Layout Fabrication Files}}   * {{:resources:fpga:xilinx:fmc:ad6673_ebz:ad6673_gerber_20_012008b.zip|AD6673-250EBZ Gerber/Layout Fabrication Files}}
 +\\
 </WRAP> </WRAP>
  
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 \\ \\
   * Questions? [[http://ez.analog.com/post!input.jspa?containerType=14&container=2061|Ask Help & Support]].   * Questions? [[http://ez.analog.com/post!input.jspa?containerType=14&container=2061|Ask Help & Support]].
 +\\
 </WRAP> </WRAP>
  
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 <WRAP round help 80%> <WRAP round help 80%>
 \\ \\
- 
   * [[http://www.vita.com/fmc.html|VITA's FMC info]]   * [[http://www.vita.com/fmc.html|VITA's FMC info]]
   * [[ez>community/fpga|Ask questions about the FPGA reference design]]   * [[ez>community/fpga|Ask questions about the FPGA reference design]]
 +\\
 </WRAP> </WRAP>
- 
resources/fpga/xilinx/interposer/ad6673.txt · Last modified: 25 Jan 2021 19:33 by Robin Getz

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