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resources:fpga:xilinx:interposer:ad5760 [28 Sep 2012 11:24] – Added common section for describing the evaluation setup and System Demonstration Platform Adrian Costina | resources:fpga:xilinx:interposer:ad5760 [30 Sep 2013 15:08] – [Reference Project Overview] Lucian Sin | ||
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====== Overview ====== | ====== Overview ====== | ||
- | This document presents the steps to setup an environment for using the **[[adi> | + | This document presents the steps to setup an environment for using the **[[adi> |
{{ : | {{ : | ||
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* [[adi>/ | * [[adi>/ | ||
* [[http:// | * [[http:// | ||
- | * [[http:// | ||
====== Getting Started ====== | ====== Getting Started ====== | ||
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* [[http:// | * [[http:// | ||
* FMC-SDP adapter board | * FMC-SDP adapter board | ||
- | * **EVAL-AD5760** evaluation board | + | * **EVAL-AD5760SDZ** evaluation board |
===== Required Software ===== | ===== Required Software ===== | ||
- | * Xilinx ISE 13.4 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack). | + | * Xilinx ISE 14.6. |
- | * [[http://micrium.com/ | + | * UART Terminal (Termite/Tera Term/Hyperterminal), |
+ | * The EVAL-AD5760 reference project for Xilinx KC705 FPGA. | ||
===== Downloads ===== | ===== Downloads ===== | ||
- | + | <WRAP round download 80%> | |
- | * {{:resources: | + | \\ |
- | + | * **AD5760 Driver:** https://github.com/ | |
- | The following table presents a short description the reference design archive contents. | + | * **AD5760 Commands:** https:// |
- | + | | |
- | ^ **Folder** ^ **Description** ^ | + | * **EDK KC705 Reference |
- | | Bit | Contains the KC705 configuration file that can be used to program the system for quick evaluation. | | + | \\ |
- | | Microblaze | Contains the EDK 13.4 project for the Microblaze softcore that will be implemented in the KC705 FPGA. | | + | </ |
- | | Software | Contains the source files of the software | + | |
- | | uCProbeInterface | Contains the uCProbe interface and the .elf symbols file used by uC-Probe to access data from the Microbalze memory. | | + | |
====== Run the Demonstration Project ====== | ====== Run the Demonstration Project ====== | ||
- | {{page> | + | ===== Hardware setup ===== |
- | + | ||
- | ===== Demonstration Project User Interface | + | |
- | + | ||
- | The following figure presents the **uC-Probe** interface that can be used for monitoring and controlling the operation of the **EVAL-AD5760SDZ** evaluation board. | + | |
- | + | ||
- | {{ : | + | |
- | The communication with the board is activated / deactivated by toggling | + | <WRAP round important 80%> |
+ | \\ | ||
+ | Before connecting | ||
+ | </ | ||
- | The value of the AD5760 //DAC Register// is changed using the slider located under the **//DAC Register Value (18-bit)//** label. The selected value is displayed in the numeric box located next to the slider. Next to it, the value that is read from the DAC register is displayed. The slider will select | + | * Use the FMC-SDP interposer |
+ | * Connect | ||
- | The value of the AD5760 | + | <WRAP round important 80%> |
+ | \\ | ||
+ | To power on the EVAL-AD5760 | ||
+ | </ | ||
- | The sliders **// | ||
- | The DAC’s output voltage is displayed | + | ===== Reference Project Overview ===== |
+ | The following commands were implemented | ||
+ | ^ Command ^ Description ^ | ||
+ | | **help?** | Displays all available commands. | | ||
+ | | **reset!** | Resets | ||
+ | | **coding=** | Selects | ||
+ | | **coding?** | Display the current coding style. | | ||
+ | | **register=** | Writes to the DAC register. Accepted values:\\ 0 .. 65535 - the value written to the DAC. | | ||
+ | | **register? | ||
+ | | **voltage=** | Sets the DAC output voltage. Accepted values:\\ -10 .. +10 - desired output voltage in volts. | | ||
+ | | **voltage? | ||
+ | | **output=** | Selects the DAC output state. Accepted | ||
+ | | **output?** | Displays the DAC output state. | | ||
+ | | **rbuf=** | Sets/resets the RBUF bit from control register. Accepted values:\\ 0 - RBUF is reset.\\ 1 - RBUF is set.(default) | | ||
+ | | **rbuf?** | Displays the value of RBUF bit from control register. | | ||
- | The values of the //Control Register’s// | ||
- | The values of the //Software Control Register’s// | + | Commands |
- | The hardware pins can be controlled by the switches under the label " | + | The following image shows a generic list of commands in a serial terminal connected to Xilinx KC705 FPGA's UART peripheral. |
+ | {{ : | ||
- | ===== Troubleshooting | + | ===== Software Project Setup ===== |
+ | {{page> | ||
- | In case there is a communication problem with the board the follwing actions can be perfomed in order to try to fix the issues: | ||
- | * Check that the evaluation board is powered as instructed in the board' | ||
- | * In uC-Probe refresh the symbols file by right-clicking on the **//System Browser//** window and selecting **//Refresh Symbols// | ||
- | * If the communication problem persists even after performing the previous steps, restart the uC-Probe application and try to run the interface again. | ||
====== More information ====== | ====== More information ====== | ||
* [[resources: | * [[resources: | ||
{{page> | {{page> |