This document presents the steps to setup an environment for using the EVAL-AD5760SDZ evaluation board together with the Xilinx KC705 FPGA board and the Xilinx Embedded Development Kit (EDK). Below is presented a picture of the EVAL-AD5760SDZ Evaluation Board with the Xilinx KC705 board.
For component evaluation and performance purposes, as opposed to quick prototyping, the user is directed to use the part evaluation setup. This consists of:
The SDP-B controller board is part of Analog Devices System Demonstration Platform (SDP). It provides a high speed USB 2.0 connection from the PC to the component evaluation board. The PC runs the evaluation software. Each evaluation board, which is an SDP compatible daughter board, includes the necessary installation file required for performance testing.
Note: it is expected that the analog performance on the two platforms may differ.
Below is presented a picture of SDP-B Controller Board with the EVAL-AD5760SDZ Evaluation Board.
The AD5760 is a true 16-bit, unbuffered voltage output DAC that operates from a bipolar supply of up to 33 V. The AD5760 accepts a positive reference input range of 5 V to VDD − 2.5 V and a negative reference input range of VSS + 2.5 V to 0 V. The AD5760 offers a relative accuracy specification of ±0.5 LSB maximum range, and operation is guaranteed monotonic with a ±0.5 LSB DNL maximum range specification.
The EVAL-AD5760 evaluation board is a full-featured evaluation board, designed to allow the user to easily evaluate all features of the AD5760 voltage output, 16-bit DAC. The AD5760 pins are accessible at on-board connectors for external connection.
The first objective is to ensure that you have all of the items needed and to install the software tools so that you are ready to create and run the evaluation project.
Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage of the KC705 is set to 3.3V. For more details on how to change the setting for VADJ_FPGA visit the Xilinx KC705 product page.
To power on the EVAL-AD5760 evaluation board, you need to provide external differential supply voltage to J2 connector(for more information see: EVAL-AD5760SDZ evaluation board user guide) and a 5V reference voltage to VREF connector on the evaluation board. VREFN will be connected to AGND (LK8 option=B, LK2 option=B, LK3 option=B, LK4 inserted).
The following commands were implemented in this version of EVAL-AD5760 reference project for Xilinx KC705 FPGA board.
|help?||Displays all available commands.|
|reset!||Resets the device.|
|coding=|| Selects the coding style. Accepted values:
0 - Two's complement coding.(default)
1 - Offset binary coding.
|coding?||Display the current coding style.|
|register=|| Writes to the DAC register. Accepted values:
0 .. 65535 - the value written to the DAC.
|register?||Displays last written value to the DAC register.|
|voltage=|| Sets the DAC output voltage. Accepted values:
-10 .. +10 - desired output voltage in volts.
|voltage?||Displays the output voltage.|
|output=|| Selects the DAC output state. Accepted values:
0 - Normal state.
1 - Clamped via 6KOhm to AGND.(default)
2 - Tristate.
|output?||Displays the DAC output state.|
|rbuf=|| Sets/resets the RBUF bit from control register. Accepted values:
0 - RBUF is reset.
1 - RBUF is set.(default)
|rbuf?||Displays the value of RBUF bit from control register.|
Commands can be executed using a serial terminal connected to the UART peripheral of Xilinx KC705 FPGA.
The hardware platform for each reference projects with FMC-SDP interposer and KC705 evaluation board is common. The next steps should be followed to recreate the software project of the reference design: