Wiki

Analog Devices Wiki

English
English
简体中文
简体中文
日本語
日本語
Руccкий
Руccкий

Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revisionPrevious revision
Next revision		Previous revision
resources:fpga:xilinx:interposer:ad5668 [22 Feb 2012 11:16] – Approved Adrian Costinaresources:fpga:xilinx:interposer:ad5668 [09 Jan 2021 00:48] (current) – user interwiki links Robin Getz
Line 13: Line 13:
 ====== Overview ====== ====== Overview ======
  
-This document presents the steps to setup an environment for using the **[[adi>AD5668|EVAL-AD5668SDZ]]** evaluation board together with the Xilinx KC705 FPGA board, the Xilinx Embedded Development Kit (EDK) and the [[http://micrium.com/page/products/tools/probe|Micrium µC-Probe]] run-time monitoring tool. Below is presented a picture of the EVAL-AD5668SDZ Evaluation Board with the Xilinx KC705 board.+This document presents the steps to setup an environment for using the **[[adi>AD5668|EVAL-AD5668SDZ]]** evaluation board together with the Xilinx KC705 FPGA board and the Xilinx Embedded Development Kit (EDK).  Below is presented a picture of the EVAL-AD5668SDZ Evaluation Board with the Xilinx KC705 board.
  
 {{ :resources:fpga:xilinx:interposer:img_ad5668.jpg }} {{ :resources:fpga:xilinx:interposer:img_ad5668.jpg }}
  
-For component evaluation and performance purposes, as opposed to quick prototyping, the user is directed to Analog Devices [[/resources/eval/sdp|System Demonstration Platform]] (**SDP**). The **SDP** consists of a: +{{page>common_sdp}}
-  * a controller board, like the **[[resources/eval/sdp/sdp-b|EVAL-SDP-CB1Z]] (SDP-B)** +
-  * a compatible Analog Devices SDP [[adi>sdp#exallist|product evaluation board]] +
-  * corresponding PC software +
-The EVAL-SDP-CB1Z controller board is part of Analog Devices SDP providing USB 2.0 high-speed connectivity to a PC computer running specific component evaluation software.  Each SDP evaluation daughter board includes the necessary installation files needed for this performance testing. It's expected that the analog performance on the two platforms may differ.+
  
 Below is presented a picture of **SDP-B** Controller Board with the **EVAL-AD5668SDZ** Evaluation Board. Below is presented a picture of **SDP-B** Controller Board with the **EVAL-AD5668SDZ** Evaluation Board.
Line 34: Line 30:
   * [[adi>AD5668|AD5668 Product Info]] - pricing, samples, datasheet   * [[adi>AD5668|AD5668 Product Info]] - pricing, samples, datasheet
   * [[adi>/static/imported-files/user_guides/UG-155.pdf|EVAL-AD5668EBZ evaluation board user guide]]   * [[adi>/static/imported-files/user_guides/UG-155.pdf|EVAL-AD5668EBZ evaluation board user guide]]
-  * [[http://www.xilinx.com/products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]] +  * [[xilinx>products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]
-  * [[http://micrium.com/page/products/tools/probe|Micrium uC-Probe]]+
  
 ====== Getting Started ====== ====== Getting Started ======
Line 43: Line 38:
 ===== Required Hardware ===== ===== Required Hardware =====
  
-  * [[http://www.xilinx.com/products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]+  * [[xilinx>products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]
   * FMC-SDP adapter board   * FMC-SDP adapter board
   * **EVAL-AD5668** evaluation board   * **EVAL-AD5668** evaluation board
Line 49: Line 44:
 ===== Required Software ===== ===== Required Software =====
  
-  * Xilinx ISE 13.4 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack). +  * Xilinx ISE 14.6. 
-  * [[http://micrium.com/page/products/tools/probe|uC-Probe]] run-time monitoring tool+  * UART Terminal (Termite/Tera Term/Hyperterminal), baud rate 115200. 
 +  * The EVAL-AD5668 reference project for Xilinx KC705 FPGA.
  
 ===== Downloads ===== ===== Downloads =====
- +<WRAP round download 80%> 
-  * {{:resources:fpga:xilinx:interposer:ad5668_evalboard.zip|Reference Design Files}} +\\ 
- +  * **AD5668 Driver:** https://github.com/analogdevicesinc/no-OS/tree/master/device_drivers/AD5629R 
-The following table presents a short description the reference design archive contents. +  * **AD5668 Commands:** https://github.com/analogdevicesinc/no-OS/tree/master/device_commands/AD5629R 
- +  * **Xilinx Boards Common Drivers:** https://github.com/analogdevicesinc/no-OS/tree/master/platform_drivers/Xilinx/SDP_Common 
-^ **Folder** ^ **Description** ^ +  * **EDK KC705 Reference project:** https://github.com/analogdevicesinc/fpgahdl_xilinx/tree/master/cf_sdp_kc705 
-| Bit | Contains the KC705 configuration file that can be used to program the system for quick evaluation. | +\\ 
-| Microblaze | Contains the EDK 13.4 project for the Microblaze softcore that will be implemented in the KC705 FPGA. | +</WRAP>
-| Software | Contains the source files of the software project that will be run by the Microblaze processor.| +
-| uCProbeInterface | Contains the uCProbe interface and the .elf symbols file used by uC-Probe to access data from the Microblaze memory. | +
 ====== Run the Demonstration Project ====== ====== Run the Demonstration Project ======
  
-{{page>ucprobe_common}}+===== Hardware setup =====
  
-===== Demonstration Project User Interface =====+<WRAP round important 80%> 
 +\\ 
 +Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage of the KC705 is set to 3.3V. For more details on how to change the setting for VADJ_FPGA visit the Xilinx KC705 product page. 
 +</WRAP>
  
-The following figure presents the **uC-Probe** interface that can be used for monitoring and controlling the operation of the **EVAL-AD5668EBZ / AD5668SD_Z** evaluation board.+  * Use the FMC-SDP interposer to connect the ADI evaluation board to the Xilinx KC705 board on the FMC LPC connector. 
 +  * Connect the JTAG and UART cables to the KC705 and power up the FPGA board.
  
-{{ :resources:fpga:altera:bemicro:ad5668interface.png?700 }}+<WRAP round important 80%> 
 +\\ 
 +To power on the EVAL-AD5668 evaluation board, you need to provide +5V supply voltage to J1 connector on the board (LK1 position=A, LK6 position=A). 
 +</WRAP>
  
-**Section A** is used to activate the board and monitor activity. The communication with the board is activated / deactivated by toggling the **ON/OFF** switch. The **Activity** LED turns green when the communication is active. If the ON/OFF switch is set to ON and the Activity LED is BLACK it means that there is a communication problem with the board. See the **Troubleshooting** section for indications on how to fix the communication problems.+===== Reference Project Overview ===== 
 +The following commands were implemented in this version of EVAL-AD5668 reference project for Xilinx KC705 FPGA board. 
 +^ Command ^ Description ^ 
 +| **help?** | Displays all available commands. | 
 +| **reset!** | Makes a power-on reset. | 
 +| **powerMode=** | Selects a given power mode for selected DAC. Accepted values:\\ channel:\\ 0 .. 7 - selected DAC A .. H.\\ power mode:\\ 0 - normal operation.\\ 1 - 1KOhm to GND.\\ 2 - 100KOhms to GND.\\ 3 - three-state. | 
 +| **powerMode?** | Displays the power mode for one selected DAC. Accepted values:\\ channel:\\ 0 .. 7 - selected DAC A .. H. | 
 +| **intRef=** | Turns on/off the internal reference. Accepted values:\\ 0 - turns off the internal reference.\\ 1 - turns on the internal reference. | 
 +| **intRef?** | Displays the status of the internal reference. | 
 +| **loadN=** | Loads selected DAC register with a given value. Accepted values:\\ channel:\\ 0 .. 7 - selected DAC A .. H.\\ 15 - all DACs.\\ value:\\ 0 .. 65535 - value to be written in register. | 
 +| **updateN** | Updates the selected DAC with the last value written in register. Accepted values:\\ channel:\\ 0 .. 7 - selected DAC A .. H.\\ 15 - all DACs.\\ value:\\ 0 .. 65535 - value to be written in register. | 
 +| **loadNUpdateN** | Loads and updates the selected DAC with a given value. Accepted values:\\ channel:\\ 0 .. 7 - selected DAC A .. H.\\ 15 - all DACs.\\ value:\\ 0 .. 65535 - value to be written in register. | 
 +| **loadNUpdateAll** | Loads the selected DAC with a given value and updates all DACs. Accepted values:\\ channel:\\ 0 .. 7 - selected DAC A .. H.\\ 15 - all DACs.\\ value:\\ 0 .. 65535 - value to be written in register. | 
 +| **enLdacPin=** | Enables/Disables the LDAC pin for selected DAC. Accepted values:\\ channel:\\ 0 .. 7 - selected DAC A .. H.\\ value:\\ 1 - disable LDAC pin.\\ 0 - enable LDAC pin. | 
 +| **enLdacPin?** | Displays the status(enabled or disabled) of the LDAC pin for a selected DAC. Accepted values:\\ channel:\\ 0 .. 7 - selected DAC A .. H. | 
 +| **clrCode=** | Loads Clear Code Register with specific clear code.\\ Accepted values:\\ 0 - clears code to zero scale when CLR pin goes from high to low.\\ 1 - clears code to midscale when CLR pin goes from high to low.\\ 2 - clears code to full scale when CLR pin goes from high to low.\\ 3 - no operation. | 
 +| **clrCode?** | Displays the active clear code. | 
 +| **ldacPin=** | Sets the output value of LDAC pin. Accepted values:\\ 0 - sets LDAC pin low.(default)\\ 1 - sets LDAC pin high. | 
 +| **ldacPin?** | Displays the value of LDAC pin. | 
 +| **clrPin=** | Sets the output value of CLR pin. Accepted values:\\ 0 - sets CLR pin low.\\ 1 - sets CLR pin high.(default) | 
 +| **clrPin?** | Displays the value of CLR pin. |
  
-**Section B** is used to set the output value on the DAC channels. In order to use this functionality, one should select the channel, select the data bits and press the **Set on DAC** switch. If the LED is active, the value will be continuously updated on the DAC. The DAC may have different reference voltages, so the user should select the value of the reference currently used. Based on this voltage, the output voltage corresponding to the data bits will be displayed.+Commands can be executed using a serial terminal connected to the UART peripheral of Xilinx KC705 FPGA.
  
-**Section C** is used to send any command to the AD5668. The command list is available in table "Command Definitions" from the [[adi>ad5668|datasheet]]. Using the sliders, the command, address and databits to be sent should be configured. After that, **Send command to DAC** switch should be activated. +The following image shows a generic list of commands in a serial terminal connected to Xilinx KC705 FPGA's UART peripheral. 
-There are two sliders used for setting the Value, one for large values and one for small values. +{{ :resources:fpga:xilinx:interposer:Terminal_KC705.jpg? }} 
- +===== Software Project Setup ===== 
-For command 4, **Power down/power up DAC**, the Channel value is used to select the power down mode: 0 for normal operation, 1 for 1k to GND, 2 for 100k to GND and 3 for Three-state operation. The least significant eight bits from the Value are used for channel selection. For additional information see [[adi>AD5668|datasheet]]. +{{page>import_workspace}}
- +
-For command 5, **Load clear code register**, the last two bits from value parameter are used as Clear code register bits. 0 will load the clear registers with 0x0000, 1 will load them with 0x8000, 2 will load them with 0xFFFF and 3 is used for no operation. +
- +
-For command 6, **Load LDAC register**, the least significant eight bits from the value are used for channel selection. If 1, the channel will consider always the LDAC active. +
- +
-For command 7, **Reset**, the value and channel parameters are not important. +
- +
-For command 8, **Set up internal REF register**, the last bit from Value is used for reference selection (0 internal reference off, other than 0 internal reference on). +
- +
-**Section D** is used to toggle the hardware pins. The functionality of the pins is described in the  [[adi>ad5668|datasheet]], table "Pin Function Descriptions". +
-When pressing the **Toggle \LDAC** switch, a HIGH to LOW and a LOW to HIGH transition will be initiated on the LDAC pin. The DAC registers will be updated with the input registers data. +
-When pressing the **Toggle \CLR** switch, a HIGH to LOW and a LOW to HIGH transition will be initiated on the CLR pin. This will update the Input registers and DAC registers with the data contained in the CLR code register: zero, midscale or full scale. Default settings clear the output to 0. +
- +
-**Section E** is used to for configuring the ADC. It is possible that the ADC to be supplied with a different voltage than the reference voltage used for the DAC case in which **ADC Supply** should be correctly configured by the user. Activating the **Continuous loop** button, the ADC will read continuously sequentially all eight channels from the DAC. If it is not active, the ADC will only read the channel selected in section B.  The voltage is computed based on the ADC Supply configuration. +
- +
-===== Troubleshooting ===== +
- +
-In case there is a communication problem with the board the follwing actions can be perfomed in order to try to fix the issues: +
-  * Check that the evaluation board is powered as instructed in the board's user guide. +
-  * In uC-Probe refresh the symbols file by right-clicking on the **//System Browser//** window and selecting **//Refresh Symbols//**. +
-  * If the communication problem persists even after performing the previous steps, restart the uC-Probe application and try to run the interface again.+
  
 ====== More information ====== ====== More information ======
-  * [[ez>community/fpga|ask questions about the FPGA reference design]] +{{page>ez_common}}
resources/fpga/xilinx/interposer/ad5668.1329905795.txt.gz · Last modified: 22 Feb 2012 11:16 by Adrian Costina

Page Tools