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resources:fpga:xilinx:interposer:ad5542a [28 Sep 2012 11:14] – Added common section for describing the evaluation setup and System Demonstration Platform Adrian Costinaresources:fpga:xilinx:interposer:ad5542a [11 Sep 2013 10:52] – changed source code (without using Micrium uC-Probe), added Sofware Setup, remove programming with Impact Lucian Sin
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 ====== Overview ====== ====== Overview ======
  
-This document presents the steps to setup an environment for using the **[[adi>AD5542A|EVAL-AD5542ASDZ]]** evaluation board together with the Xilinx KC705 FPGA board, the Xilinx Embedded Development Kit (EDK) and the [[http://micrium.com/page/products/tools/probe|Micrium µC-Probe]] run-time monitoring tool. Below is presented a picture of the EVAL-AD5542ASDZ Evaluation Board with the Xilinx KC705 board.+This document presents the steps to setup an environment for using the **[[adi>AD5542A|EVAL-AD5542ASDZ]]** evaluation board together with the Xilinx KC705 FPGA board and the Xilinx Embedded Development Kit (EDK). Below is presented a picture of the EVAL-AD5542ASDZ Evaluation Board with the Xilinx KC705 board.
  
 {{ :resources:fpga:xilinx:interposer:img_ad5542A.jpg }} {{ :resources:fpga:xilinx:interposer:img_ad5542A.jpg }}
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   * {{:resources:fpga:altera:bemicro:ad5542a_ug.pdf|EVAL-AD5542ASDZ evaluation board user guide}}   * {{:resources:fpga:altera:bemicro:ad5542a_ug.pdf|EVAL-AD5542ASDZ evaluation board user guide}}
   * [[http://www.xilinx.com/products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]   * [[http://www.xilinx.com/products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]
-  * [[http://micrium.com/page/products/tools/probe|Micrium uC-Probe]] 
  
 ====== Getting Started ====== ====== Getting Started ======
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 ===== Required Software ===== ===== Required Software =====
  
-  * Xilinx ISE 13.4 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack). +  * Xilinx ISE 14.6. 
-  * [[http://micrium.com/page/products/tools/probe|uC-Probe]] run-time monitoring tool+  * UART Terminal (Termite/Tera Term/Hyperterminal), baud rate 115200. 
 +  * The EVAL-AD5542A reference project for Xilinx KC705 FPGA.
  
 ===== Downloads ===== ===== Downloads =====
 +<WRAP round download 80%>
 +\\
 +  * {{:resources:fpga:xilinx:interposer:cf_ad5542a_kc705.zip|Reference Design Files}}
 +  * **AD5542A Driver:** https://github.com/analogdevicesinc/no-OS/tree/master/device_drivers/AD5542A
 +  * **AD5542A Commands:** https://github.com/analogdevicesinc/no-OS/tree/master/device_commands/AD5542A
 +  * **Xilinx Boards Common Drivers:** https://github.com/analogdevicesinc/no-OS/tree/master/platform_drivers/Xilinx/SDP_Common
 +  * **EDK KC705 Reference project:** https://github.com/analogdevicesinc/fpgahdl_xilinx/tree/master/cf_sdp_kc705
 +\\
 +</WRAP>
  
-  * {{:resources:fpga:xilinx:interposer:ad5542A_evalboard.zip|Reference Design Files}} 
  
-The following table presents a short description the reference design archive contents.+===== Hardware setup =====
  
-^ **Folder** ^ **Description** ^ +<WRAP round important 80%> 
-| Bit | Contains the KC705 configuration file that can be used to program the system for quick evaluation. | +\\ 
-| Microblaze | Contains the EDK 13.4 project for the Microblaze softcore that will be implemented in the KC705 FPGA. | +Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage of the KC705 is set to 3.3V. For more details on how to change the setting for VADJ_FPGA visit the Xilinx KC705 product page. 
-| Software | Contains the source files of the software project that will be run by the Microblaze processor.| +</WRAP>
-| uCProbeInterface | Contains the uCProbe interface and the .elf symbols file used by uC-Probe to access data from the Microblaze memory. |+
  
-====== Run the Demonstration Project ======+  * Use the FMC-SDP interposer to connect the ADI evaluation board to the Xilinx KC705 board on the FMC LPC connector. 
 +  * Connect the JTAG and UART cables to the KC705 and power up the FPGA board.
  
-{{page>ucprobe_common}}+<WRAP round important 80%> 
 +\\ 
 +To power on the EVAL-AD5542A evaluation board, you need to provide external +5V and -5V supply voltage. 
 +</WRAP>
  
-===== Demonstration Project User Interface =====+===== Quick start evaluation ===== 
 +For a quick start evaluation, run the **download.bat** script located in the **SDK/SDK_Workspace/bin** folder provided within the Reference Design Files.  This script uses XMD to program the FPGA with the HDL Reference Design and download the Software Reference Design into the DDR.
  
-The following figure presents the **uC-Probe** interface that can be used for monitoring and controlling the operation of the **EVAL-AD5542ASDZ** evaluation board.+<WRAP round info 80%> 
 +\\ 
 +The **download.bat** script assumes that the Xilinx ISE Design Suite 14.6 is installed at this path: **C:/Xilinx/14.6**. If the installation path on your computer is different, please modify the script accordingly. 
 +</WRAP>
  
-{{ :resources:fpga:altera:bemicro:ad5542a_interface.png?700 }}+If programming was successful, you should be seeing the command messages appear on the terminal.
  
-  * The communication with the board is activated / deactivated by toggling the **//ON/OFF//** switch. The **//Activity//** LED turns green when the communication is active. If the **//ON/OFF//** switch is set to **//ON//** and the **//Activity//** LED is **//BLACK//** it means that there is a communication problem with the board. See the **Troubleshooting** section for indications on how to fix the communication problems.  +===== Reference Project Overview ===== 
-  * The **//DAC//** switch is used to enable/disable the input of the 74HCT244 octal buffer present on the evaluation board. When the switch is pressed the buffer’s input is enabled and it is possible to communicate with the DAC on SPI. +The following commands were implemented in this version of EVAL-AD5542A reference project for Xilinx KC705 FPGA board. 
-  * The **//LDAC//** switch is used to control the LDAC signal of the AD5542A. When the switch is pressed the DAC register is updated with the contents of the serial register data. +^ Command ^ Description ^ 
-  * The **//CLR//** switch is used to control the Asynchronous Clear Input of the AD5542A. When the CLR switch is active all LDAC pulses are ignored. When the CLR switch is deactivated the DAC register is cleared to the model selectable midscale. +| **help?** | Displays all available commands. | 
-  * The **//DAC Value//** slider is used to set the value to be loaded into the DAC register. The selected value is displayed in the numeric box next to the slider.+| **register=** | Writes to the DAC register. Accepted values:\\ 0 .. 65535 -  the value written to the DAC. | 
 +| **register?** | Displays last written value in the DAC register. | 
 +| **voltage=** | Sets the DAC output voltage. Accepted values:\\ -2500 .. +2500 - desired output voltage in milivolts. | 
 +| **voltage?** | Displays last written voltage value to the DAC. | 
 +| **ldacPin=** | Sets the output value of LDAC pin. Accepted values:\\ 0 - sets LDAC pin low.(default)\\ 1 - sets LDAC pin high. | 
 +| **ldacPin?** | Displays the value of LDAC pin. |  
 +| **clrPin=** | Sets the output value of CLR pin. Accepted values:\\ 0 - sets CLR pin low.\\ 1 - sets CLR pin high.(default) |  
 +| **clrPin?** | Displays the value of CLR pin. |
  
-===== Troubleshooting ===== 
  
-In case there is a communication problem with the board the follwing actions can be perfomed in order to try to fix the issues: +Commands can be executed using a serial terminal connected to the UART peripheral of Xilinx KC705 FPGA. 
-  * Check that the evaluation board is powered as instructed in the board's user guide. + 
-  * In uC-Probe refresh the symbols file by right-clicking on the **//System Browser//** window and selecting **//Refresh Symbols//**. +The following image shows a generic list of commands in a serial terminal connected to Xilinx KC705 FPGA's UART peripheral. 
-  * If the communication problem persists even after performing the previous steps, restart the uC-Probe application and try to run the interface again.+{{ :resources:fpga:xilinx:interposer:Terminal_KC705.jpg? }} 
 + 
 + 
 +===== Software Project Setup ===== 
 +{{page>import_workspace}}
  
 ====== More information ====== ====== More information ======
   * [[resources:tools-software:linux-drivers:iio-dac:ad5446|AD5542A IIO DAC Linux Driver]]   * [[resources:tools-software:linux-drivers:iio-dac:ad5446|AD5542A IIO DAC Linux Driver]]
 {{page>ez_common}} {{page>ez_common}}
resources/fpga/xilinx/interposer/ad5542a.txt · Last modified: 09 Jan 2021 00:48 by Robin Getz

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