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resources:fpga:xilinx:interposer:ad5415 [16 Feb 2012 14:11] – [Downloads] Andrei Cozmaresources:fpga:xilinx:interposer:ad5415 [09 Jan 2021 00:48] (current) – user interwiki links Robin Getz
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 ===== Evaluation Boards ===== ===== Evaluation Boards =====
  
-  * [[adi>EVAL-AD5415SDZ]]+  * [[adi>EVAL-AD5415|EVAL-AD5415SDZ]]
  
 ====== Overview ====== ====== Overview ======
  
-This document presents the steps to setup an environment for using the **[[adi>AD5415|EVAL-AD5415SDZ]]** evaluation board together with the Xilinx KC705 FPGA boardthe Xilinx Embedded Development Kit (EDK) and the [[http://micrium.com/page/products/tools/probe|Micrium μC-Probe]] run-time monitoring tool. Below is presented a picture of the EVAL-AD5415SDZ Evaluation Board with the Xilinx KC705 board.+This document presents the steps to setup an environment for using the **[[adi>AD5415|EVAL-AD5415SDZ]]** evaluation board together with the Xilinx KC705 FPGA board and the Xilinx Embedded Development Kit (EDK). Below is presented a picture of the EVAL-AD5415SDZ Evaluation Board with the Xilinx KC705 board.
  
 {{ :resources:fpga:xilinx:interposer:img_ad5415.jpg?400 }} {{ :resources:fpga:xilinx:interposer:img_ad5415.jpg?400 }}
  
-For component evaluation and performance purposes, as opposed to quick prototyping, the user is directed to Analog Devices [[/resources/eval/sdp|System Demonstration Platform]] (**SDP**). The **SDP** consists of a: +{{page>common_sdp}}
-  * a controller board, like the **[[resources/eval/sdp/sdp-b|EVAL-SDP-CB1Z]] (SDP-B)** +
-  * a compatible Analog Devices SDP [[adi>sdp#exallist|product evaluation board]] +
-  * corresponding PC software +
-The EVAL-SDP-CB1Z controller board is part of Analog Devices SDP providing USB 2.0 high-speed connectivity to a PC computer running specific component evaluation software.  Each SDP evaluation daughter board includes the necessary installation files needed for this performance testing. It's expected that the analog performance on the two platforms may differ.+
  
 Below is presented a picture of **SDP-B** Controller Board with the **EVAL-AD5415SDZ** Evaluation Board. Below is presented a picture of **SDP-B** Controller Board with the **EVAL-AD5415SDZ** Evaluation Board.
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-The **EVAL-AD5415** evaluation board is designed to help customers quickly prototype new AD5415 circuits and reduce design time. The board requires ±12 V and +5 V supplies. The +12 V VDD and −12 V VSS are used to power the output amplifier; the +5 V supply is used to power the DAC (VDD) and transceivers (VCC).+The **EVAL-AD5415** evaluation board is designed to help customers quickly prototype new AD5415 circuits and reduce design time. The board requires ±12 V and +5 V supplies.
  
 ===== More information ===== ===== More information =====
   * [[adi>AD5415|AD5415 Product Info]] - pricing, samples, datasheet   * [[adi>AD5415|AD5415 Product Info]] - pricing, samples, datasheet
   * [[adi>/static/imported-files/user_guides/UG-296.pdf|EVAL-AD5415SDZ evaluation board user guide]]   * [[adi>/static/imported-files/user_guides/UG-296.pdf|EVAL-AD5415SDZ evaluation board user guide]]
-  * [[http://www.xilinx.com/products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]] +  * [[xilinx>products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]
-  * [[http://micrium.com/page/products/tools/probe|Micrium uC-Probe]]+
  
 ====== Getting Started ====== ====== Getting Started ======
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 ===== Required Hardware ===== ===== Required Hardware =====
  
-  * [[http://www.xilinx.com/products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]+  * [[xilinx>products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]
   * FMC-SDP adapter board   * FMC-SDP adapter board
   * **EVAL-AD5415** evaluation board   * **EVAL-AD5415** evaluation board
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 ===== Required Software ===== ===== Required Software =====
  
-  * Xilinx ISE 13.4 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack)+  * Xilinx ISE 14.6
-  * [[http://micrium.com/page/products/tools/probe|uC-Probe]] run-time monitoring tool+  * UART Terminal (Termite/Tera Term/Hyperterminal), baud rate 115200. 
 +  * The EVAL-AD5415 reference project for Xilinx KC705 FPGA. 
  
 ===== Downloads ===== ===== Downloads =====
 +<WRAP round download 80%>
 +\\
 +  * **AD5415 Driver:** https://github.com/analogdevicesinc/no-OS/tree/master/device_drivers/AD5449
 +  * **AD5415 Commands:** https://github.com/analogdevicesinc/no-OS/tree/master/device_commands/AD5449
 +  * **Xilinx Boards Common Drivers:** https://github.com/analogdevicesinc/no-OS/tree/master/platform_drivers/Xilinx/SDP_Common
 +  * **EDK KC705 Reference project:** https://github.com/analogdevicesinc/fpgahdl_xilinx/tree/master/cf_sdp_kc705
 +\\
 +</WRAP>
 +===== Hardware setup =====
  
-  * {{:resources:fpga:xilinx:interposer:ad5415_evalboard.zip|Reference Design Files}}+<WRAP round important 80%> 
 +\\ 
 +Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage of the KC705 is set to 3.3V. For more details on how to change the setting for VADJ_FPGA visit the Xilinx KC705 product page. 
 +</WRAP>
  
-The following table presents a short description the reference design archive contents.+  * Use the FMC-SDP interposer to connect the ADI evaluation board to the Xilinx KC705 board on the FMC LPC connector. 
 +  * Connect the JTAG and UART cables to the KC705 and power up the FPGA board.
  
-^ **Folder** ^ **Description** ^ +<WRAP round important 80%> 
-| Bit | Contains the KC705 configuration file that can be used to program the system for quick evaluation. | +\\ 
-| Microblaze | Contains the EDK 13.4 project for the Microblaze softcore that will be implemented in the KC705 FPGA. | +To power on the EVAL-AD5415 evaluation board, you need to provide external +12V VDD and -12V VSS supply voltage used to power the output amplifier (for more information see: [[adi>/static/imported-files/user_guides/UG-296.pdf|EVAL-AD5415SDZ evaluation board user guide]]) and a +5V supply used to power the DAC and transceivers. 
-| Software | Contains the source files of the software project that will be run by the Microblaze processor.| +</WRAP>
-| uCProbeInterface | Contains the uCProbe interface and the .elf symbols file used by uC-Probe to access data from the Microbalze memory|+
  
-====== Run the Demonstration Project ======+===== Reference Project Overview ===== 
 +The following commands were implemented in this version of EVAL-AD5415 reference project for Xilinx KC705 FPGA board. 
 +^ Command ^ Description ^ 
 +| **help?** | Displays all available commands. | 
 +| **load=** | Loads selected DAC input register with a given value. Accepted values:\\ channel:\\ 0 - select DAC A input register.\\ 1 - select DAC B input register.\\ value:\\ 0 .. 4095 - value to be written in register. | 
 +| **loadAll=** | Loads both DAC input registers. Accepted values:\\ 0 .. 4095 - value to be written in register. | 
 +| **loadAndUpdate=** | Loads and updates the selected DAC with a given value. Accepted values:\\ channel:\\ 0 - select DAC A.\\ 1 - select DAC B.\\ value:\\ 0 .. 4095 - value to be written in register. | 
 +| **updateAll!** | Updates both DAC outputs. | 
 +| **readback?** | Reads from the selected DAC register. Accepted values:\\ channel:\\ 0 - read from DAC A.\\ 1 - read from DAC B. | 
 +| **clearToZero!** | Clears both DAC outputs to zero scale. | 
 +| **clearToMid!** | Clears both DAC outputs to midscale. | 
 +| **ldacPin=** | Sets the output value of LDAC pin. Accepted values:\\ 0 - sets LDAC pin low.(default)\\ 1 - sets LDAC pin high. | 
 +| **ldacPin?** | Displays the value of LDAC pin. | 
 +| **clrPin=** | Sets the output value of CLR pin. Accepted values:\\ 
 +| **clrPin?** | Displays the value of CLR pin. |
  
-{{page>ucprobe_common}} 
  
-===== Demonstration Project User Interface ===== 
  
-The following figure presents the **uC-Probe** interface that can be used for monitoring and controlling the operation of the **EVAL-AD5415** evaluation board.+Commands can be executed using a serial terminal connected to the UART peripheral of Xilinx KC705 FPGA.
  
-{{ :resources:fpga:altera:bemicro:ad5415_interface.png?700 }}+The following image shows a generic list of commands in a serial terminal connected to Xilinx KC705 FPGA's UART peripheral. 
 +{{ :resources:fpga:xilinx:interposer:Terminal_KC705.jpg? }}
  
-**Section A** is used to activate the board and monitor activity. The communication with the board is activated / deactivated by toggling the **//ON/OFF//** switch. The **//Activity//** LED turns green when the communication is active. If the **//ON/OFF//** switch is set to **//ON//** and the **//Activity//** LED is **//BLACK//** it means that there is a communication problem with the board.+===== Software Project Setup ===== 
 +{{page>import_workspace}}
  
-**Section B** is used to control the state of the hardware pins (**//CLR//** and **//LDAC//**). 
- 
-**Section C** is used to call the clear functions (clear DAC output to zero scale or to midscale). 
- 
-**Section D** is used to change the bits from the Control Register. After any change of the buttons position is necessary to press the (**//Send Control Bits//**  button. 
- 
-**Section E** is used to load, update and read the DACs registers. 
- 
-===== Troubleshooting ===== 
- 
-In case there is a communication problem with the board the follwing actions can be perfomed in order to try to fix the issues: 
-  * Check that the evaluation board is powered as instructed in the board's user guide. 
-  * In uC-Probe refresh the symbols file by right-clicking on the **//System Browser//** window and selecting **//Refresh Symbols//**.  
-  * If the communication problem persists even after performing the previous steps, restart the uC-Probe application and try to run the interface again. 
  
 ====== More information ====== ====== More information ======
-  * [[ez>community/fpga|ask questions about the FPGA reference design]] +{{page>ez_common}}
resources/fpga/xilinx/interposer/ad5415.1329397901.txt.gz · Last modified: 16 Feb 2012 14:11 by Andrei Cozma