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resources:fpga:xilinx:interposer:ad5272 [28 May 2012 15:52] – Approved Alexandru.Tofanresources:fpga:xilinx:interposer:ad5272 [10 Oct 2013 13:18] – changed source code (without Micrium uC-Probe), added Software Setup, remove programming with Impact Lucian Sin
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   * [[adi>AD5272]]   * [[adi>AD5272]]
 +  * [[adi>AD5274]]
  
 ===== Evaluation Boards ===== ===== Evaluation Boards =====
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 ====== Overview ====== ====== Overview ======
  
-This document presents the steps to setup an environment for using the **[[adi>AD5272|EVAL-AD5272SDZ]]** evaluation board together with the Xilinx KC705 FPGA board, the Xilinx Embedded Development Kit (EDK) and the [[http://micrium.com/page/products/tools/probe|Micrium µC-Probe]] run-time monitoring tool. Below is presented a picture of the EVAL-AD5272SDZ Evaluation Board with the Xilinx KC705 board.+This document presents the steps to setup an environment for using the **[[adi>AD5272|EVAL-AD5272SDZ]]** evaluation board together with the Xilinx KC705 FPGA board and the Xilinx Embedded Development Kit (EDK). Below is presented a picture of the EVAL-AD5272SDZ Evaluation Board with the Xilinx KC705 board.
  
 {{ :resources:fpga:xilinx:interposer:ad5272.jpg?400 }} {{ :resources:fpga:xilinx:interposer:ad5272.jpg?400 }}
  
-For component evaluation and performance purposes, as opposed to quick prototyping, the user is directed to Analog Devices [[/resources/eval/sdp|System Demonstration Platform]] (**SDP**). The **SDP** consists of a: +{{page>common_sdp}}
-  * a controller board, like the **[[resources/eval/sdp/sdp-b|EVAL-SDP-CB1Z]] (SDP-B)** +
-  * a compatible Analog Devices SDP [[adi>sdp#exallist|product evaluation board]] +
-  * corresponding PC software +
-The EVAL-SDP-CB1Z controller board is part of Analog Devices SDP providing USB 2.0 high-speed connectivity to a PC computer running specific component evaluation software.  Each SDP evaluation daughter board includes the necessary installation files needed for this performance testing. It's expected that the analog performance on the two platforms may differ.+
  
 Below is presented a picture of **SDP-B** Controller Board with the **EVAL-AD5272SDZ** Evaluation Board. Below is presented a picture of **SDP-B** Controller Board with the **EVAL-AD5272SDZ** Evaluation Board.
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   * [[adi>/static/imported-files/user_guides/UG-094.pdf|EVAL-AD5272SDZ evaluation board user guide]]   * [[adi>/static/imported-files/user_guides/UG-094.pdf|EVAL-AD5272SDZ evaluation board user guide]]
   * [[http://www.xilinx.com/products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]   * [[http://www.xilinx.com/products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]
-  * [[http://micrium.com/page/products/tools/probe|Micrium uC-Probe]] 
  
 ====== Getting Started ====== ====== Getting Started ======
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 ===== Required Software ===== ===== Required Software =====
  
-  * Xilinx ISE 13.4 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack). +  * Xilinx ISE 14.6. 
-  * [[http://micrium.com/page/products/tools/probe|uC-Probe]] run-time monitoring tool+  * UART Terminal (Termite/Tera Term/Hyperterminal), baud rate 115200. 
 +  * The EVAL-AD5272 reference project for Xilinx KC705 FPGA. 
  
 ===== Downloads ===== ===== Downloads =====
- +<WRAP round download 80%> 
-  * {{:resources:fpga:xilinx:interposer:ad5272_evalboard.zip|Reference Design Files}} +\\ 
- +  * **AD5272 Driver:** https://github.com/analogdevicesinc/no-OS/tree/master/device_drivers/AD5270 
-The following table presents a short description the reference design archive contents. +  * **AD5272 Commands:** https://github.com/analogdevicesinc/no-OS/tree/master/device_commands/AD5270 
- +  * **Xilinx Boards Common Drivers:** https://github.com/analogdevicesinc/no-OS/tree/master/platform_drivers/Xilinx/SDP_Common 
-^ **Folder** ^ **Description** ^ +  * **EDK KC705 Reference project:** https://github.com/analogdevicesinc/fpgahdl_xilinx/tree/master/cf_sdp_kc705 
-| Bit | Contains the KC705 configuration file that can be used to program the system for quick evaluation. | +\\ 
-| Microblaze | Contains the EDK 13.4 project for the Microblaze softcore that will be implemented in the KC705 FPGA. | +</WRAP>
-| Software | Contains the source files of the software project that will be run by the Microblaze processor.| +
-| uCProbeInterface | Contains the uCProbe interface and the .elf symbols file used by uC-Probe to access data from the Microbalze memory. | +
 ====== Run the Demonstration Project ====== ====== Run the Demonstration Project ======
  
-{{page>ucprobe_common}} +===== Hardware setup =====
- +
-===== Demonstration Project User Interface ===== +
- +
-The following figure presents the **uC-Probe** interface that can be used for monitoring and controlling the operation of the **EVAL-AD5272SDZ** evaluation board. +
- +
-{{ :resources:fpga:altera:bemicro:ad5272interface.png?700 }} +
- +
-**Section A** is used to activate the board and monitor activity. The communication with the board is activated / deactivated by toggling the **//ON/OFF//** switch. The **//Activity//** LED turns green when the communication is active. If the **//ON/OFF//** switch is set to **//ON//** and the **//Activity//** LED is **//BLACK//** it means that there is a communication problem with the board. See the **Troubleshooting** section for indications on how to fix the communication problems. +
- +
-**Section B** displays the data that is read from the RDAC register. +
- +
-**Section C** is used to write data to RDAC register. +
- +
-**Section D** allows access to the control register, enabling or disabling the resistor performance mode, RDAC write protection, and the 50-TP memory.+
  
-  * 50-TP Program – enables/disables device for 50-TP program. +<WRAP round important 80%> 
-  * RDAC Write Protect – allows or not update of wiper position through a digital interface. +\\ 
-  * Resistor Performance – enables/disables resistor tolerance calibration.+Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage of the KC705 is set to 3.3V. For more details on how to change the setting for VADJ_FPGA visit the Xilinx KC705 product page. 
 +</WRAP>
  
-**Section E** is used to reset and to shutdown the device.+  * Use the FMC-SDP interposer to connect the ADI evaluation board to the Xilinx KC705 board on the FMC LPC connector. 
 +  * Connect the JTAG and UART cables to the KC705 and power up the FPGA board.
  
-  * Soft Reset – sends a reset by software. +===== Reference Project Overview ===== 
-  * Hard Reset – sends a reset by hardware. +The following commands were implemented in this version of EVAL-AD5272 reference project for Xilinx KC705 FPGA board. 
-  * Power Down – powers down the part.+^ Command ^ Description ^ 
 +| **help?** | Displays all available commands. | 
 +| **reset!**| Makes a software reset of the device. | 
 +| **rdac=** | Writes to the RDAC register. Accepted values:\\ 0 .. 1024 (0 .. 255 for AD5274) - the value written to RDAC. | 
 +| **rdac?** | Displays the last written value in RDAC register. | 
 +| **store!** | Stores the RDAC setting to 50-TP. | 
 +| **50TPValue?** | Displays the contents of the selected 50-TP register. Accepted values:\\ 0 .. 50 - selected 50-TP register. | 
 +| **50TPAddress?** | Displays the address of the last programmed 50-TP register. | 
 +| **power=** | Turns on/off the device. Accepted values:\\ 1 - normal mode.(default)\\ 0 - shutdown mode. | 
 +| **power?** | Displays the power status of the device. |
  
-**Section F** is used read/write the 50-TP memory.+Commands can be executed using a serial terminal connected to the UART peripheral of Xilinx KC705 FPGA.
  
-  * Blow Fuse – blows the actual RDAC register data in the 50-TP memory. +The following image shows a generic list of commands in a serial terminal connected to Xilinx KC705 FPGA's UART peripheral. 
-  * Read Fuse Content – reads content of 50-TP memory. +{{ :resources:fpga:xilinx:interposer:Terminal_KC705.jpg? }}
-  * Read Fuse Address – reads address of the last 50-TP programmed memory location.+
  
-===== Troubleshooting =====+===== Software Project Setup ===== 
 +{{page>import_workspace}}
  
-In case there is a communication problem with the board the follwing actions can be perfomed in order to try to fix the issues: 
-  * Check that the evaluation board is powered as instructed in the board's user guide. 
-  * In uC-Probe refresh the symbols file by right-clicking on the **//System Browser//** window and selecting **//Refresh Symbols//**. 
-  * If the communication problem persists even after performing the previous steps, restart the uC-Probe application and try to run the interface again. 
  
 ====== More information ====== ====== More information ======
   * [[resources:tools-software:linux-drivers:misc:dpot|AD5272 Digital Potentiometer Linux Driver]]   * [[resources:tools-software:linux-drivers:misc:dpot|AD5272 Digital Potentiometer Linux Driver]]
 {{page>ez_common}} {{page>ez_common}}
resources/fpga/xilinx/interposer/ad5272.txt · Last modified: 09 Jan 2021 00:48 by Robin Getz

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