This document presents the steps to setup an environment for using the EVAL-AD2S1205SDZ evaluation board together with the Xilinx KC705 FPGA board and the Xilinx Embedded Development Kit (EDK). Below is presented a picture of the EVAL-AD2S1205CBZ Evaluation Board with the Xilinx KC705 board.
For component evaluation and performance purposes, as opposed to quick prototyping, the user is directed to use the part evaluation setup. This consists of:
The SDP-B controller board is part of Analog Devices System Demonstration Platform (SDP). It provides a high speed USB 2.0 connection from the PC to the component evaluation board. The PC runs the evaluation software. Each evaluation board, which is an SDP compatible daughter board, includes the necessary installation file required for performance testing.
Note: it is expected that the analog performance on the two platforms may differ.
Below is presented a picture of SDP-B Controller Board with the EVAL-AD2S1205SDZ Evaluation Board.
The EVAL-AD2S1205SDZ evaluation board is a member of a growing number of boards available for the SDP. It was designed to help customers evaluate performance or quickly prototype new AD2S1205 circuits and reduce design time.
The AD2S1205 is a complete 12-bit resolution tracking resolver-to-digital converter that contains an on-board programmable sinusoidal oscillator providing sine wave excitation for resolvers. The converter accepts 3.15 V p-p ± 27% input signals on the Sin and Cos inputs. A Type II tracking loop is employed to track the inputs and convert the input Sin and Cos information into a digital representation of the input angle and velocity. The maximum tracking rate is a function of the external clock frequency. The performance of the AD2S105 is specified across a frequency range of 8.192 MHz ± 25%, allowing a maximum tracking rate of 1250 rps.
The first objective is to ensure that you have all of the items needed and to install the software tools so that you are ready to create and run the evaluation project.
Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage of the KC705 is set to 3.3V. For more details on how to change the setting for VADJ_FPGA visit the Xilinx KC705 product page.
The following commands were implemented in this version of EVAL-AD2S1205 reference project for Xilinx KC705 FPGA board.
|help?||Displays all available commands.|
|position?||Displays the current angular position.|
|velocity?||Displays the current angular velocity.|
Commands can be executed using a serial terminal connected to the UART peripheral of Xilinx KC705 FPGA.
The following image shows a generic list of commands in a serial terminal connected to Xilinx KC705 FPGA's UART peripheral.
The hardware platform for each reference projects with FMC-SDP interposer and KC705 evaluation board is common. The next steps should be followed to recreate the software project of the reference design: