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— | resources:fpga:xilinx:fmc:fmc-imageon [29 Sep 2017 09:34] – [Supported Carriers] Added FMC slot specification Adrian Costina | ||
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+ | ====== FMC-IMAGEON Xilinx Reference Design ====== | ||
+ | |||
+ | ===== Introduction ===== | ||
+ | |||
+ | The [[https:// | ||
+ | |||
+ | ===== Supported Devices ===== | ||
+ | |||
+ | * [[https:// | ||
+ | |||
+ | ===== Supported Carriers ===== | ||
+ | |||
+ | * [[xilinx> | ||
+ | * [[http:// | ||
+ | |||
+ | |||
+ | |||
+ | ==== Required Hardware ==== | ||
+ | |||
+ | * One of the supported carrier and FMC-IMAGEON boards. | ||
+ | * HDMI Monitor (should be capable of supporting 1080p and/or 720p for the demo files). | ||
+ | |||
+ | ==== Required Software ==== | ||
+ | |||
+ | * We upgrade the Xilinx tools on every release. The supported version number can be found in our [[https:// | ||
+ | * A UART terminal (Tera Term/ | ||
+ | |||
+ | |||
+ | |||
+ | |||
+ | |||
+ | ===== Using the reference design ===== | ||
+ | |||
+ | ==== Functional description ==== | ||
+ | |||
+ | |{{.: | ||
+ | |||
+ | The reference design consists of two independent pcore modules. | ||
+ | |||
+ | The video part consists of a Xilinx VDMA interface and the ADV7511/ | ||
+ | |||
+ | ==== Video Transmit (VDMA to HDMI) ==== | ||
+ | |||
+ | In the transmit direction, the VDMA streams frame data to this core. The internal buffers of this pcore are small (1k) and do NOT buffer any frames as such. Additional resources may cause loss of synchronization due to DDR bandwidth requirements. The video core is capable of supporting any formats through a set of parameter registers (given below). The pixel clock is generated internal to the device and must be configured for the correct pixel frequency. It also allows a programmable color pattern for debug purposes. A zero to one transition on the enable bits trigger the corresponding action for HDMI enable and color pattern enable. | ||
+ | |||
+ | The reference design defaults to the 1080p video mode. Users may change the video settings by programming the video size registers. The core requires a corresponding pixel clock to generate the video. This clock must be generated externally. | ||
+ | |||
+ | Note that the pixel frequency for 1080p is 148.5MHz. | ||
+ | |||
+ | The reference design reads 24bits of RGB data from DDR and performs color space conversion (RGB to YCbCr) and down sampling (444 to 422). If bypassed, the lower 16bits of DDR data is passed to the HDMI interface as it is. | ||
+ | |||
+ | A color pattern register provides a quick check of any RGB values on the monitor. If enabled, the register data is used as the pixel data for the entire frame. | ||
+ | |||
+ | ==== Video Receive (HDMI to VDMA) ==== | ||
+ | |||
+ | In the receive direction, the HDMI data is first decoded and the synchronization signals are generated. The core then streams video data to VDMA. The internal buffers of this pcore are small (1k) and do NOT buffer any frames as such. Additional resources may cause loss of synchronization due to DDR bandwidth requirements. The video core is capable of supporting any formats through a set of parameter registers (given below). The core runs at the pixel clock from ADV7611. | ||
+ | |||
+ | The core decodes the active video size from the received data and compares it against an expected video size. If they do not match, the core will NOT stream data to VDMA to avoid possible lock up conditions in the VDMA core due to byte length mismatches. Also, the reference design performs color space conversion (YCbCr to RGB) and up sampling (422 to 444). If bypassed, the lower 16bits of DDR data is passed to the VDMA interface as it is. | ||
+ | |||
+ | Test pattern generators and monitors are provided at each interface and clock domain boundaries. The default configuration is in loop back mode with the HDMI interface acting as a direct pass through. | ||
+ | |||
+ | ==== Audio ==== | ||
+ | |||
+ | The audio part consists of a Xilinx DMA interface and the ADV7511 spdif audio interface. The audio clock is derived from the bus clock. A programmable register (see below) controls the division factor. The audio data is read from the DDR as two 16bit words for the left and right channels. It is then transmitted on the SPDIF frame. The sample frequency and format may be controlled using the registers below. The reference design defaults to 48KHz. | ||
+ | |||
+ | ==== Registers ==== | ||
+ | |||
+ | Please refer to the regmap.txt file inside the pcores. | ||
+ | |||
+ | ==== Audio Registers (axi_spdif_tx) ==== | ||
+ | |||
+ | ^ QW Address< | ||
+ | | 0x00 | 23:20| 0 | mode | Sample format 0 to 8 (0-16bit, 8-24bit). | | ||
+ | | | 15:8 | 0 | ratio | Clock divider for the transmit frequency = bus_clock/ | ||
+ | | | 1 | 0 | txdata | ||
+ | | | 0 | 0 | txenable | ||
+ | | 0x01 | 7:6 | 0 | frequency | ||
+ | | | 3 | 0 | gstat | Generation status original/ | ||
+ | | | 2 | 0 | pre-emphasis | ||
+ | | | 1 | 0 | copy | Copy permitted (0x1) or inhibited (0x0) (RO). | | ||
+ | | | 0 | 0 | audio | Data format is non-audio (0x1) or audio (0x0) (RO). | | ||
+ | | 1. For AXI-Lite byte addresses, multiply by 4. ||||| | ||
+ | |||
+ | |||
+ | ===== Using the ADV7511 Transmitter Library ===== | ||
+ | |||
+ | The transmitter library is a collection of APIs that provide a consistent interface to ADV7511. | ||
+ | The library is a software layer that sits between the application and the TX hardware. The library is intended to serve two purposes: | ||
+ | * Provide the application with a set of APIs that can be used to configure HDMI TX hardware without the need for low-level register access. This makes the application portable across different revisions of the hardware and even across different hardware modules. | ||
+ | * Provide basic services to aid the application in controlling the TX module, such as interrupt service routine, HDCP high-level control and status information. | ||
+ | |||
+ | The Demo project uses the ADV7511 Transmitter Library. | ||
+ | The project is an example of how to: | ||
+ | * Initialize the ADV7511 High-Definition Multimedia Interface (HDMI®) transmitter. | ||
+ | * Check current AVR operating mode and depending on this result set the AV mute state. | ||
+ | * Display an image and play a sound. | ||
+ | |||
+ | The project contains 2 components: the Demo project files and the ADV7511 Transmitter Library. All the components have to be downloaded from the links provided in the **Downloads** section. | ||
+ | |||
+ | ==== Software Setup ==== | ||
+ | The **ADV7511 Transmitter Library Demo** contains a folder called // | ||
+ | These are the steps that need to be followed to recreate the software project: | ||
+ | * Copy the // | ||
+ | * Copy the library file to the // | ||
+ | {{: | ||
+ | * Copy the library headers to the // | ||
+ | {{: | ||
+ | * Copy the ADV7511 Transmitter Library Demo files to the // | ||
+ | {{: | ||
+ | * Open the Xilinx SDK. When the SDK starts it asks for a to provide a folder where to store the workspace. Any folder can be provided. | ||
+ | * In the SDK select the // | ||
+ | {{: | ||
+ | * In the //Import// window select the // | ||
+ | {{: | ||
+ | * In the //Import Projects// window select the // | ||
+ | {{: | ||
+ | * The //Project Explorer// window now shows the projects that exist in the workspace and the files for each project. The SDK should automatically build the projects and the //Console// window will display the the result of the build. If the build is not done automatically select the // | ||
+ | {{: | ||
+ | |||
+ | |||
+ | ===== Downloads ===== | ||
+ | |||
+ | **HDL Reference Designs:** | ||
+ | |||
+ | <WRAP round download 80%> | ||
+ | * **ML605: ** {{: | ||
+ | * **Zed: ** {{: | ||
+ | * **ADV7511 Transmitter Library Demo: ** {{: | ||
+ | </ | ||
+ | |||
+ | **ADV7511 Transmitter Library Demo Software** | ||
+ | <WRAP round download 80%> | ||
+ | \\ | ||
+ | * **ADV7511 Transmitter Library: ** https:// | ||
+ | * **ADV7511 Transmitter Library Demo files: ** https:// | ||
+ | </ | ||
+ | |||
+ | <WRAP round help 80%> | ||
+ | * Questions? [[https:// | ||
+ | </ | ||
+ | |||
+ | |||
+ | ===== Tar file contents ===== | ||
+ | |||
+ | The tar file contains, in most cases, the following files and/or directories. To rebuild the reference design simply double click the XMP file and run the tool. To build SDK, select a workspace and use the C file to build the elf file. Please refer to [[http:// | ||
+ | |||
+ | | license.txt | ADI license & copyright information. | | ||
+ | | system.mhs | ||
+ | | system.xmp | ||
+ | | data/ | UCF file and/or DDR MIG project files. | | ||
+ | | docs/ | Documentation files (Please note that this wiki page is the documentation for the reference design). | | ||
+ | | sw/ | Software (Xilinx SDK) & bit file(s). | | ||
+ | | cf_lib/ | ||
+ | |||