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resources:fpga:xilinx:fmc:ad9467 [07 Jan 2015 17:31] – Update page with Vivado support, fix ZED tar.gz Istvan Csomortani | resources:fpga:xilinx:fmc:ad9467 [19 Apr 2024 11:59] (current) – Add reference to AD9467/Zed using ACE iulia Moldovan | ||
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===== Introduction ===== | ===== Introduction ===== | ||
- | The [[adi> | + | The [[adi> |
- | ===== Supported Devices ===== | ||
- | * [[adi> | + | ===== Supported devices ===== |
- | {{: | + | |
- | ===== Supported Carriers ===== | + | * [[adi> |
- | ^ Board ^ XPS ^ Vivado | ||
- | | [[xilinx> | ||
- | | [[xilinx> | ||
- | | [[xilinx> | ||
- | | [[http:// | ||
- | Board]] | **x** | **x** | | ||
- | <WRAP round important 80%> | + | ===== Supported carriers ===== |
- | \\ | + | |
- | The XPS projects remain on this website only for legacy purposes. The support for them has been discontinued. | + | |
- | </ | + | |
- | ===== Quick Start Guide ===== | + | * [[xilinx> |
+ | * [[https:// | ||
- | The reference | + | ===== Block design |
- | ==== Required Hardware | + | ==== Xilinx block diagram |
- | * ML605/ | + | {{: |
- | * AD9467-FMC-EBZ board | + | |
- | * Signal generator (for data) | + | |
- | * Signal generator (for clock) (optional) | + | |
+ | ==== AD9467 FMC card block diagram ==== | ||
+ | {{: | ||
- | ==== Required Software ==== | ||
- | * Xilinx ISE Design Suite 14.4 | ||
- | * Vivado Design Suite 2014.2 | ||
- | * A UART terminal (Tera Term/ | ||
- | ==== Running Demo (SDK) Program | + | ==== Description |
- | To begin, connect the AD9467-FMC-EBZ board to the FMC-LPC connector of ML605 (see image below) or KC705 or Zed board. If using VC707 connect to the FMC1-HPC. Connect power and two USB cables from the PC to the //JTAG// and //UART// USB connectors on the edge of the ML605. ** The demo program uses the default board configuration that uses an external clock (AD9517 is powered down). ** However, since AD9517 is still access-able via SPI, the SDK program configures it for a pass through mode. Connect a clock source to the CLKIN SMA connector and a signal source to the AIN SMA connector of the FMC card. After the hardware setup, turn the power on to the ML605. | + | |
- | {{: | + | The reference design is built on a ARM/ |
- | Run the **// | + | Through an SPI interface, |
- | **Note: | + | The LVDS interface captures and buffers data from the ADC. The DMA interface then transfers |
- | If programming was successful, you should be seeing messages appear on the terminal as shown in figure below. | ||
- | {{: | + | ==== Clock selection ==== |
- | The reference design contains an example on how to: | + | The board provides three (some modification maybe necessary) possible clock paths for clocking |
- | * Initialize the AD9467 evaluation | + | |
- | * Initialize | + | |
- | * Test the ADC communication using the test patterns and PRBS sequences generated by the AD9467 | + | |
- | * Capture data from the AD9467 using DMA transfers | + | |
- | After the ADC test patterns and PRBS sequences are verified, if no errors are present, the reference design continuously reads data from the ADC. The ADC data can be viewed using the Chipscope project located in the "// | + | === Default clock input === |
- | * open Chipscope and press the **//Open Cable/ | + | |
- | * open the // | + | |
- | * start the data capture | + | |
- | This is how the output of the ADC looks like. | + | |
- | {{:resources: | + | The **default clock input** circuitry is derived from a simple transformer-coupled circuit using a high bandwidth 1:1 impedance ratio transformer (T201) that adds a very low amount of jitter to the clock path. The clock input (J201) is 50 Ω terminated and AC-coupled to handle single-ended sine wave types of inputs. The transformer converts |
- | ===== Using the HDL reference design ===== | + | |
- | ==== Functional description ==== | + | === Crystal oscillator |
- | The reference design | + | The evaluation board can be set up to be clocked from the **crystal oscillator**, |
+ | * Install C205 and C206 | ||
+ | * Remove C202 | ||
+ | Jumper P200 is used to disable the oscillator from running. \\ | ||
- | {{: | + | === Clock generator AD9517 === |
- | The reference design consists of three functional modules, a LVDS interface, a PN9/PN23/PAT monitor and a DMA interface. | + | A **differential LVPECL or LVDS clock driver** can also be used to clock the ADC input using the [[adi> |
+ | * Populate (C304, C305) for LVPECL clock driver **or** (C306, C307) for LVDS clock driver, with 0.1 µF capacitors | ||
+ | * Remove C209 and C210 to disconnect the default clock path inputs | ||
- | The LVDS interface captures and buffers data from the ADC. The DMA interface then transfers the samples to the external DDR-DRAM. The capture is initiated by the software. The status of capture (overflow, over the range) | + | The AD9517 has many SPI-selectable options that are set to a default mode of operation. Consult |
+ | <WRAP round important 100%> | ||
+ | Please make sure you have removed or inserted the corresponding components on the board to select the desired clock path. The schematic of the board can be found {{ : | ||
+ | </ | ||
- | ==== Registers ==== | ||
- | Refer to the **// | + | ==== Hardware description ==== |
- | ==== Good To Know ==== | + | To find out more information about the [[adi> |
- | The PN9/PN23 sequences are not compatible with O.150. Please use the equations given in the reference design. They follow the polynomial equations as in O.150, but ONLY the msb is inverted. | + | {{: |
- | The AD9467 drives the interleaved first byte (D15:D1) on the rising edge and second byte (D14:D0) on the falling edge of DCO clock. However in certain frequencies the captured data (from IDDR) seems to be reverse. If that occurs try setting the " | ||
- | ==== Clock Selection | + | ===== Quick start guide ===== |
- | The board provides three (some modification maybe necessary) possible clock path for clocking the AD9467. | + | ==== Required hardware ==== |
- | * External passive clock (default): A SMA connector is provided for an external clock source. | + | * [[https://www.avnet.com/ |
- | * Optional active | + | * [[adi> |
- | * Optional oscillator: The connector P200 must be set to OSC-ON position. This can be enabled through the passive or active | + | * Signal/clock generator |
+ | * Signal generator (analog input, | ||
+ | * Signal synthesizer | ||
- | **Please make sure you have removed or inserted | + | ==== Required software ==== |
+ | |||
+ | | ||
+ | | ||
+ | |||
+ | ===== Using the HDL reference design ===== | ||
+ | |||
+ | Check this wiki page if you're not familiar about [[: | ||
+ | |||
+ | The PN9/PN23 sequences are not compatible with O.150. Please use the equations given in the reference design. They follow the polynomial equations as in O.150, but ONLY the msb is inverted. | ||
+ | |||
+ | The AD9467 drives the interleaved first byte (D15: | ||
===== Using the Software Reference Design ===== | ===== Using the Software Reference Design ===== | ||
Line 107: | Line 100: | ||
* Capture data from the AD9467 using DMA transfers | * Capture data from the AD9467 using DMA transfers | ||
- | The software project contains 3 components: the AD9467-FMC-EBZ reference design files, the AD9467 driver and the AD9517 driver. All the components have to be downloaded from the links provided in the **Downloads** section. | + | The software project contains 3 components: the AD9467-FMC-EBZ reference design files, the AD9467 driver and the AD9517 driver. All the components have to be downloaded from the links provided in the [[/ |
==== AD9467 Software Driver ==== | ==== AD9467 Software Driver ==== | ||
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==== Software Setup ==== | ==== Software Setup ==== | ||
- | The **HDL Reference Design** for each supported Xilinx FPGA board contains a folder called // | + | <WRAP round info 100%> |
- | These are the steps that need to be followed to recreate the software | + | Instruction about how to create a software |
- | * Copy the // | + | </WRAP> |
- | * Copy the no-OS drivers source code to the // | + | |
- | {{: | + | |
- | * Open the Xilinx SDK. When the SDK starts it asks you to provide a folder where to store the workspace. Any folder | + | |
- | * In the SDK select the //**File-> | + | |
- | {{: | + | |
- | * In the //Import// window select the // | + | |
- | {{: | + | |
- | * In the //Import Projects// window select the // | + | |
- | {{: | + | |
- | * The //Project Explorer// window now shows the projects that exist in the workspace and the files for each project. The SDK should automatically build the projects and the //Console// window will display the result of the build. If the build is not done automatically select the // | + | |
- | {{: | + | |
- | * At this point the software project setup is complete, the FPGA can be programmed and the software can be downloaded into the system. | + | |
- | The example code is located | + | <note important> |
- | + | **Board Files:** | |
- | ===== Downloads ===== | + | <WRAP round download> |
- | + | * {{: | |
- | The HDL Reference Designs and the no-OS Software can be downloaded from the Analog Devices github.\\ | + | * {{:resources: |
- | \\ | + | * {{ :resources: |
- | <WRAP round important 80%> | + | |
- | Only Xilinx coregen xco files are provided with the HDL Reference Design. You must regenerate | + | |
- | \\ | + | |
- | The software project contains 3 components: the AD9467-FMC-EBZ reference design files, the AD9467 driver and the AD9517 driver. All the components have to be downloaded from the links below. | + | |
</ | </ | ||
- | **HDL Reference Designs:** | ||
- | <WRAP round download 80%> | + | ===== Resources ===== |
- | **Sources for ISE** | + | |
- | * **ML605 | + | * [[repo> |
- | | + | |
- | * **VC707 HDL Reference Design: | + | * [[adi> |
- | * **ZED HDL Reference Design: ** {{: | + | * {{: |
+ | * [[repo> | ||
+ | | ||
+ | | ||
+ | | ||
+ | * [[https://github.com/ | ||
+ | * [[https://github.com/ | ||
- | **Sources for Vivado** | ||
- | * **ZED HDL Reference Design: ** https:// | ||
- | * **KC705 HDL Reference Design: ** https:// | ||
- | </ | ||
- | **no-OS Software: | + | ===== More information ===== |
- | <WRAP round download 80%> | + | |
- | * **AD9467 Driver: | + | |
- | * **AD9517 Driver: | + | |
- | * **AD9467-FMC-EBZ Reference Design: ** https:// | + | |
- | </ | + | |
- | **Board Files:** | + | |
- | <WRAP round download 80%> | + | * [[: |
- | * {{: | + | * [[: |
- | * {{: | + | * [[: |
- | * {{: | + | * [[:resources: |
- | **Note:** C302 and C303 are not installed as indicated in the Schematic and BOM. | + | * [[: |
- | </ | + | |
- | <WRAP round help 80%> | ||
- | \\ | ||
- | * Questions? [[http:// | ||
- | \\ | ||
- | </ | ||
+ | ===== Support ===== | ||
- | ==== Reference Design Contents ==== | + | Analog Devices will provide **limited** online support for anyone using the reference design with Analog Devices components via the [[ez> |
- | <WRAP round important 80%> | + | It should be noted, |
- | \\ | + | |
- | The information below is valid just in case of the XPS projects. The XPS projects remain on this website only for legacy purposes. The support for them has been discontinued. | + | |
- | </ | + | |
- | + | ||
- | ^ HDL Reference Design | + | |
- | | license.txt | ADI license & copyright information. | | + | |
- | | system.mhs | + | |
- | | system.xmp | + | |
- | | data/ | UCF file and/or DDR MIG project files. | | + | |
- | | docs/ | Documentation files (Please note that this wiki page is the documentation for the reference design). | | + | |
- | | Chipscope/ | + | |
- | | ../ | + | |
- | ^ Software Reference Design | + | |
- | | cf_ad9467.h | Header file containing the registers definitions for the AD9467 HDL core. | | + | |
- | | cf_ad9467.c | Implementation of the AD9467 HDL core access functions | + | |
- | | spi.h | Header file for the Xilinx AXI SPI driver. | | + | |
- | | spi.c | Implementation file for the Xilinx AXI SPI driver. | | + | |
- | | main.c | Implementation of the program' | + | |
- | ^ AD9467 Software Driver | + | |
- | | AD9467.h | AD9467 software driver header file. | | + | |
- | | AD9467.c | AD9467 software driver implementation file. | | + | |
- | ^ AD9517 Software Driver | + | |
- | | AD9517.h | AD9517 software driver header file. | | + | |
- | | AD9517_cfg.h | AD9517 software driver configuration file. | | + | |
- | | AD9517.c | AD9517 software driver implementation file. | | + | |
- | ===== More information ===== | + | |
- | <WRAP round help 80%> | + | |
- | \\ | + | |
- | [[ez> | + | |
- | </ | + |