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+ | ====== AD9467 Native FMC Card / Xilinx Reference Design ====== | ||
+ | ===== Introduction ===== | ||
+ | |||
+ | The [[adi> | ||
+ | |||
+ | ===== Supported Devices ===== | ||
+ | |||
+ | * [[adi> | ||
+ | {{: | ||
+ | |||
+ | ===== Supported Carriers ===== | ||
+ | |||
+ | ^ Board ^ XPS ^ Vivado | ||
+ | | [[xilinx> | ||
+ | | [[xilinx> | ||
+ | | [[xilinx> | ||
+ | | [[http:// | ||
+ | Board]] | **DISCONTINUED** | ||
+ | |||
+ | <WRAP round important 80%> | ||
+ | \\ | ||
+ | The XPS projects remain on this website only for legacy purposes. The support for them has been discontinued. | ||
+ | </ | ||
+ | |||
+ | ===== Quick Start Guide ===== | ||
+ | |||
+ | The reference design has been tested with ML605, KC705, VC707 and Zed. The notes below refer to ML605, the procedure is same for the other boards. Please make sure you are using the correct reference design for the board(s) that you have. | ||
+ | |||
+ | ==== Required Hardware ==== | ||
+ | * ML605/ | ||
+ | * AD9467-FMC-EBZ board | ||
+ | * Signal generator (for data) | ||
+ | * Signal generator (for clock) (optional) | ||
+ | |||
+ | |||
+ | ==== Required Software ==== | ||
+ | |||
+ | * We're upgrade the Xilinx tools on every release. The supported version number can be found in our [[https:// | ||
+ | * A UART terminal (Tera Term/ | ||
+ | |||
+ | ==== Running Demo (SDK) Program ==== | ||
+ | To begin, connect the AD9467-FMC-EBZ board to the FMC-LPC connector of ML605 (see image below) or KC705 or Zed board. If using VC707 connect to the FMC1-HPC. Connect power and two USB cables from the PC to the //JTAG// and //UART// USB connectors on the edge of the ML605. ** The demo program uses the default board configuration that uses an external clock (AD9517 is powered down). ** However, since AD9517 is still access-able via SPI, the SDK program configures it for a pass through mode. Connect a clock source to the CLKIN SMA connector and a signal source to the AIN SMA connector of the FMC card. After the hardware setup, turn the power on to the ML605. | ||
+ | |||
+ | {{: | ||
+ | |||
+ | Run the **// | ||
+ | |||
+ | **Note:** The // | ||
+ | |||
+ | If programming was successful, you should be seeing messages appear on the terminal as shown in figure below. | ||
+ | |||
+ | {{: | ||
+ | |||
+ | The reference design contains an example on how to: | ||
+ | * Initialize the AD9467 evaluation board | ||
+ | * Initialize the AD9467 HDL core | ||
+ | * Test the ADC communication using the test patterns and PRBS sequences generated by the AD9467 | ||
+ | * Capture data from the AD9467 using DMA transfers | ||
+ | |||
+ | After the ADC test patterns and PRBS sequences are verified, if no errors are present, the reference design continuously reads data from the ADC. The ADC data can be viewed using the Chipscope project located in the "// | ||
+ | * open Chipscope and press the **//Open Cable/ | ||
+ | * open the // | ||
+ | * start the data capture | ||
+ | This is how the output of the ADC looks like. | ||
+ | |||
+ | {{: | ||
+ | ===== Using the HDL reference design ===== | ||
+ | |||
+ | ==== Functional description ==== | ||
+ | |||
+ | The reference design is built on a Microblaze based system parameterized for Linux. A functional block diagram of the design is given below. | ||
+ | |||
+ | {{: | ||
+ | |||
+ | The reference design consists of three functional modules, a LVDS interface, a PN9/ | ||
+ | |||
+ | The LVDS interface captures and buffers data from the ADC. The DMA interface then transfers the samples to the external DDR-DRAM. The capture is initiated by the software. The status of capture (overflow, over the range) are reported back to the software. | ||
+ | |||
+ | |||
+ | ==== Registers ==== | ||
+ | |||
+ | Refer to the **// | ||
+ | |||
+ | ==== Good To Know ==== | ||
+ | |||
+ | The PN9/PN23 sequences are not compatible with O.150. Please use the equations given in the reference design. They follow the polynomial equations as in O.150, but ONLY the msb is inverted. | ||
+ | |||
+ | The AD9467 drives the interleaved first byte (D15:D1) on the rising edge and second byte (D14:D0) on the falling edge of DCO clock. However in certain frequencies the captured data (from IDDR) seems to be reverse. If that occurs try setting the " | ||
+ | |||
+ | ==== Clock Selection ==== | ||
+ | |||
+ | The board provides three (some modification maybe necessary) possible clock path for clocking the AD9467. | ||
+ | |||
+ | * External passive clock (default): A SMA connector is provided for an external clock source. | ||
+ | * Optional active clock path or using the AD9517 : You may use either the PECL (OUT3) or the LVDS (OUT5) outputs. The optional oscillator may be used as a clock source for the AD9517 REF or CLK inputs. | ||
+ | * Optional oscillator: The connector P200 must be set to OSC-ON position. This can be enabled through the passive or active (AD9517) path. | ||
+ | |||
+ | **Please make sure you have removed or inserted the corresponding components on the board to select the desired clock path.** | ||
+ | |||
+ | ===== Using the Software Reference Design ===== | ||
+ | |||
+ | The Software Reference Design contains an example on how to: | ||
+ | * Initialize the AD9467 evaluation board | ||
+ | * Initialize the AD9467 HDL core | ||
+ | * Test the ADC communication using the test patterns and PRBS sequences generated by the AD9467 | ||
+ | * Capture data from the AD9467 using DMA transfers | ||
+ | |||
+ | The software project contains 3 components: the AD9467-FMC-EBZ reference design files, the AD9467 driver and the AD9517 driver. All the components have to be downloaded from the links provided in the **Downloads** section. | ||
+ | ==== AD9467 Software Driver ==== | ||
+ | |||
+ | Below is presented a short description of all the functions provided in the driver. | ||
+ | |||
+ | |< 100% 40% 60% >| | ||
+ | ^ Function | ||
+ | | int32_t **// | ||
+ | | int32_t **// | ||
+ | | int32_t **// | ||
+ | | int32_t **// | ||
+ | | int32_t **// | ||
+ | | int32_t **// | ||
+ | | int32_t **// | ||
+ | | int32_t **// | ||
+ | | int32_t **// | ||
+ | | int32_t **// | ||
+ | | int32_t **// | ||
+ | | int32_t **// | ||
+ | | int32_t **// | ||
+ | | int32_t **// | ||
+ | | int32_t **// | ||
+ | | int32_t **// | ||
+ | | int32_t **// | ||
+ | | float **// | ||
+ | | int32_t **// | ||
+ | | int32_t **// | ||
+ | | int32_t **// | ||
+ | | int32_t **// | ||
+ | |||
+ | ==== Software Setup ==== | ||
+ | |||
+ | The **HDL Reference Design** for each supported Xilinx FPGA board contains a folder called // | ||
+ | These are the steps that need to be followed to recreate the software project: | ||
+ | * Copy the // | ||
+ | * Copy the no-OS drivers source code to the // | ||
+ | {{: | ||
+ | * Open the Xilinx SDK. When the SDK starts it asks you to provide a folder where to store the workspace. Any folder can be provided. | ||
+ | * In the SDK select the // | ||
+ | {{: | ||
+ | * In the //Import// window select the // | ||
+ | {{: | ||
+ | * In the //Import Projects// window select the // | ||
+ | {{: | ||
+ | * The //Project Explorer// window now shows the projects that exist in the workspace and the files for each project. The SDK should automatically build the projects and the //Console// window will display the result of the build. If the build is not done automatically select the // | ||
+ | {{: | ||
+ | * At this point the software project setup is complete, the FPGA can be programmed and the software can be downloaded into the system. | ||
+ | |||
+ | The example code is located in the ”// | ||
+ | |||
+ | | ||
+ | ===== Downloads ===== | ||
+ | |||
+ | The HDL Reference Designs and the no-OS Software can be downloaded from the Analog Devices github.\\ | ||
+ | \\ | ||
+ | <WRAP round important 80%> | ||
+ | Only Xilinx coregen xco files are provided with the HDL Reference Design. You must regenerate the IP core files using this file. See [[http:// | ||
+ | \\ | ||
+ | The software project contains 3 components: the AD9467-FMC-EBZ reference design files, the AD9467 driver and the AD9517 driver. All the components have to be downloaded from the links below. | ||
+ | </ | ||
+ | |||
+ | **HDL Reference Designs:** | ||
+ | |||
+ | <WRAP round download 80%> | ||
+ | **Sources for ISE** | ||
+ | |||
+ | * **ML605 HDL Reference Design: ** {{: | ||
+ | * **KC705 HDL Reference Design: ** {{: | ||
+ | * **VC707 HDL Reference Design: ** {{: | ||
+ | * **ZED HDL Reference Design: | ||
+ | |||
+ | **Sources for Vivado** | ||
+ | * **ZED HDL Reference Design: ** https:// | ||
+ | * **KC705 HDL Reference Design: ** https:// | ||
+ | </ | ||
+ | |||
+ | **no-OS Software:** | ||
+ | <WRAP round download 80%> | ||
+ | * **AD9467 Driver: | ||
+ | * **AD9517 Driver: | ||
+ | * **AD9467-FMC-EBZ Reference Design: ** https:// | ||
+ | </ | ||
+ | |||
+ | **Board Files:** | ||
+ | <WRAP round download 80%> | ||
+ | * {{: | ||
+ | * {{: | ||
+ | * {{: | ||
+ | **Note:** C302 and C303 are not installed as indicated in the Schematic and BOM. | ||
+ | </ | ||
+ | |||
+ | ==== Reference Design Contents ==== | ||
+ | |||
+ | <WRAP round important 80%> | ||
+ | \\ | ||
+ | The information below is valid just in case of the XPS projects. The XPS projects remain on this website only for legacy purposes. The support for them has been discontinued. | ||
+ | </ | ||
+ | |||
+ | ^ HDL Reference Design | ||
+ | | license.txt | ADI license & copyright information. | | ||
+ | | system.mhs | ||
+ | | system.xmp | ||
+ | | data/ | UCF file and/or DDR MIG project files. | | ||
+ | | docs/ | Documentation files (Please note that this wiki page is the documentation for the reference design). | | ||
+ | | Chipscope/ | ||
+ | | ../ | ||
+ | ^ Software Reference Design | ||
+ | | cf_ad9467.h | Header file containing the registers definitions for the AD9467 HDL core. | | ||
+ | | cf_ad9467.c | Implementation of the AD9467 HDL core access functions and ADC test and capture functions. | | ||
+ | | spi.h | Header file for the Xilinx AXI SPI driver. | | ||
+ | | spi.c | Implementation file for the Xilinx AXI SPI driver. | | ||
+ | | main.c | Implementation of the program' | ||
+ | ^ AD9467 Software Driver | ||
+ | | AD9467.h | AD9467 software driver header file. | | ||
+ | | AD9467.c | AD9467 software driver implementation file. | | ||
+ | ^ AD9517 Software Driver | ||
+ | | AD9517.h | AD9517 software driver header file. | | ||
+ | | AD9517_cfg.h | AD9517 software driver configuration file. | | ||
+ | | AD9517.c | AD9517 software driver implementation file. | | ||
+ | ===== More information ===== | ||
+ | <WRAP round help 80%> | ||
+ | \\ | ||
+ | [[ez> | ||
+ | </ |