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resources:fpga:xilinx:fmc:ad9467 [25 Jun 2014 15:55] – [AD9467 Native FMC Card / Xilinx Reference Designs] Jillian Walsh | resources:fpga:xilinx:fmc:ad9467 [20 Apr 2020 13:32] – updated 9467fmc01c.zip file to remove specific email address Umesh Jayamohan | ||
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The [[adi> | The [[adi> | ||
- | ===== Supported Devices | + | ===== Evaluation Board Hardware |
+ | |||
+ | To find out more information about the [[http:// | ||
- | * [[adi> | ||
{{: | {{: | ||
- | ===== Supported Carriers ===== | + | ==== Clock Selection |
- | * [[xilinx> | + | The board provides three (some modification maybe necessary) possible clock path for clocking the AD9467. |
- | * [[xilinx> | + | |
- | * [[xilinx> | + | |
- | * [[http:// | + | |
+ | The **default clock input** circuitry is derived from a simple transformer-coupled circuit using a high bandwidth 1:1 impedance ratio transformer (T201) that adds a very low amount of jitter to the clock path. The clock input (J201) is 50 Ω terminated and ac-coupled to handle single-ended sine wave types of inputs. The transformer converts the single-ended input to a differential signal that is clipped before entering the ADC clock inputs. | ||
- | ===== Quick Start Guide ===== | + | The evaluation board can be set up to be clocked from the **crystal oscillator**, |
- | The reference design has been tested with ML605, KC705, VC707 and Zed. The notes below refer to ML605, the procedure is same for the other boards. Please make sure you are using the correct reference design | + | A **differential LVPECL or LVDS clock driver** can also be used to clock the ADC input using the [[http:// |
- | ==== Required Hardware ==== | + | <WRAP round important 100%> |
- | * ML605/ | + | \\ |
- | * AD9467-FMC-EBZ | + | Please make sure you have removed or inserted |
- | * Signal generator (for data) | + | </ |
- | * Signal generator (for clock) (optional) | + | |
+ | ===== Supported Carriers ===== | ||
- | ==== Required Software ==== | + | |
- | | + | * [[http://www.zedboard.org| ZedBoard]] |
- | * A UART terminal (Tera Term/Hyperterminal), | + | |
- | ==== Running Demo (SDK) Program | + | ==== Other Required Hardware |
- | To begin, connect the AD9467-FMC-EBZ board to the FMC-LPC connector of ML605 (see image below) or KC705 or Zed board. If using VC707 connect to the FMC1-HPC. Connect power and two USB cables from the PC to the //JTAG// and //UART// USB connectors on the edge of the ML605. ** The demo program uses the default board configuration that uses an external clock (AD9517 is powered down). ** However, since AD9517 is still access-able via SPI, the SDK program configures it for a pass through mode. Connect a clock source to the CLKIN SMA connector and a signal source to the AIN SMA connector of the FMC card. After the hardware setup, turn the power on to the ML605. | + | |
- | {{: | + | * Signal synthesizer (for data and/or clock input). |
- | Run the **// | + | ==== Required |
- | **Note:** The //download.bat// script assumes that the //Xilinx ISE Design Suite 14.4// is installed at this path: // | + | |
+ | * A UART terminal (Tera Term/Hyperterminal), | ||
- | If programming was successful, you should be seeing messages appear on the terminal as shown in figure below. | + | ===== Using the HDL reference design ===== |
- | {{:resources:fpga: | + | <WRAP round info 100%> |
+ | Instruction about how to build the HDL design and generate a bit stream can be found [[https:// | ||
+ | </ | ||
- | The reference design contains an example on how to: | + | ==== Functional description ==== |
- | * Initialize the AD9467 evaluation board | + | |
- | * Initialize the AD9467 HDL core | + | |
- | * Test the ADC communication using the test patterns and PRBS sequences generated by the AD9467 | + | |
- | * Capture data from the AD9467 using DMA transfers | + | |
- | After the ADC test patterns and PRBS sequences are verified, if no errors are present, the reference design | + | The reference design |
- | * open Chipscope and press the **//Open Cable/ | + | |
- | * open the // | + | |
- | * start the data capture | + | |
- | This is how the output of the ADC looks like. | + | |
- | {{: | + | === Xilinx block diagram === |
- | ===== Using the HDL reference design ===== | + | {{: |
- | ==== Functional description ==== | + | === AD9467 FMC Card block diagram |
+ | {{: | ||
- | The reference design is built on a Microblaze based system parameterized for Linux. A functional block diagram of the design is given below. | ||
- | {{: | + | Through an SPI interface, |
- | + | ||
- | The reference design consists of three functional modules, a LVDS interface, | + | |
The LVDS interface captures and buffers data from the ADC. The DMA interface then transfers the samples to the external DDR-DRAM. The capture is initiated by the software. The status of capture (overflow, over the range) are reported back to the software. | The LVDS interface captures and buffers data from the ADC. The DMA interface then transfers the samples to the external DDR-DRAM. The capture is initiated by the software. The status of capture (overflow, over the range) are reported back to the software. | ||
- | |||
- | |||
- | ==== Registers ==== | ||
- | |||
- | Refer to the **// | ||
==== Good To Know ==== | ==== Good To Know ==== | ||
Line 81: | Line 66: | ||
The AD9467 drives the interleaved first byte (D15:D1) on the rising edge and second byte (D14:D0) on the falling edge of DCO clock. However in certain frequencies the captured data (from IDDR) seems to be reverse. If that occurs try setting the " | The AD9467 drives the interleaved first byte (D15:D1) on the rising edge and second byte (D14:D0) on the falling edge of DCO clock. However in certain frequencies the captured data (from IDDR) seems to be reverse. If that occurs try setting the " | ||
- | |||
- | ==== Clock Selection ==== | ||
- | |||
- | The board provides three (some modification maybe necessary) possible clock path for clocking the AD9467. | ||
- | |||
- | * External passive clock (default): A SMA connector is provided for an external clock source. | ||
- | * Optional active clock path or using the AD9517 : You may use either the PECL (OUT3) or the LVDS (OUT5) outputs. The optional oscillator may be used as a clock source for the AD9517 REF or CLK inputs. | ||
- | * Optional oscillator: The connector P200 must be set to OSC-ON position. This can be enabled through the passive or active (AD9517) path. | ||
- | |||
- | Please make sure you have removed or inserted the corresponding components on the board to select the desired clock path. | ||
===== Using the Software Reference Design ===== | ===== Using the Software Reference Design ===== | ||
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* Capture data from the AD9467 using DMA transfers | * Capture data from the AD9467 using DMA transfers | ||
- | The software project contains 3 components: the AD9467-FMC-EBZ reference design files, the AD9467 driver and the AD9517 driver. All the components have to be downloaded from the links provided in the **Downloads** section. | + | The software project contains 3 components: the AD9467-FMC-EBZ reference design files, the AD9467 driver and the AD9517 driver. All the components have to be downloaded from the links provided in the [[http:// |
==== AD9467 Software Driver ==== | ==== AD9467 Software Driver ==== | ||
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==== Software Setup ==== | ==== Software Setup ==== | ||
- | The **HDL Reference Design** for each supported Xilinx FPGA board contains | + | <WRAP round info 100%> |
- | These are the steps that need to be followed to recreate the software project: | + | Instruction about how to create |
- | * Copy the //**SDK_Workspace**// | + | </WRAP> |
- | * Copy the no-OS drivers source code to the //**SDK_Workspace/ | + | |
- | {{: | + | |
- | * Open the Xilinx SDK. When the SDK starts it asks you to provide a folder where to store the workspace. Any folder can be provided. | + | |
- | * In the SDK select the // | + | |
- | {{: | + | |
- | * In the //Import// window select the // | + | |
- | {{: | + | |
- | * In the //Import Projects// window select the // | + | |
- | {{: | + | |
- | * The //Project Explorer// window now shows the projects that exist in the workspace and the files for each project. The SDK should automatically build the projects and the //Console// window will display the result of the build. If the build is not done automatically select the // | + | |
- | {{: | + | |
- | * At this point the software project setup is complete, the FPGA can be programmed and the software can be downloaded into the system. | + | |
- | + | ||
- | The example code is located in the ”// | + | |
+ | The exact location of the no-OS source files can be found in the [[http:// | ||
| | ||
===== Downloads ===== | ===== Downloads ===== | ||
- | The HDL Reference Designs and the no-OS Software can be downloaded from the Analog Devices github.\\ | + | The HDL Reference Designs and the no-OS Software can be downloaded from the Analog Devices github. |
- | \\ | + | |
- | <WRAP round important 80%> | + | |
- | Only Xilinx coregen xco files are provided with the HDL Reference Design. You must regenerate the IP core files using this file. See [[http:// | + | |
- | \\ | + | |
- | The software project contains 3 components: the AD9467-FMC-EBZ reference design files, the AD9467 driver and the AD9517 driver. All the components have to be downloaded from the links below. | + | |
- | </ | + | |
**HDL Reference Designs:** | **HDL Reference Designs:** | ||
- | <WRAP round download | + | <WRAP round download> |
- | * **ML605 HDL Reference Design: | + | **latest release** |
- | * **KC705 HDL Reference Design: ** {{:resources: | + | * **ZED HDL Reference Design: ** https://github.com/ |
- | * **VC707 HDL Reference Design: ** {{:resources: | + | * **KC705 HDL Reference Design: ** https://github.com/ |
- | * **ZED HDL Reference Design: | + | |
</ | </ | ||
**no-OS Software:** | **no-OS Software:** | ||
- | <WRAP round download | + | <WRAP round download> |
- | * **AD9467 Driver: | + | **latest release** |
- | * **AD9517 Driver: | + | * **AD9467 Driver: |
- | * **AD9467-FMC-EBZ Reference Design: ** https:// | + | * **AD9517 Driver: |
+ | * **AD9467-FMC-EBZ Reference Design: ** https:// | ||
</ | </ | ||
**Board Files:** | **Board Files:** | ||
- | <WRAP round download | + | <WRAP round download> |
* {{: | * {{: | ||
* {{: | * {{: | ||
- | * {{: | + | * {{ : |
+ | **Note:** C302 and C303 are not installed as indicated in the Schematic and BOM. | ||
</ | </ | ||
+ | ===== More information ===== | ||
- | <WRAP round help 80%> | ||
- | \\ | ||
- | * Questions? [[http:// | ||
- | \\ | ||
- | </ | ||
- | |||
- | |||
- | ==== Reference Design Contents ==== | ||
- | |||
- | ^ HDL Reference Design | ||
- | | license.txt | ADI license & copyright information. | | ||
- | | system.mhs | ||
- | | system.xmp | ||
- | | data/ | UCF file and/or DDR MIG project files. | | ||
- | | docs/ | Documentation files (Please note that this wiki page is the documentation for the reference design). | | ||
- | | Chipscope/ | ||
- | | ../ | ||
- | ^ Software Reference Design | ||
- | | cf_ad9467.h | Header file containing the registers definitions for the AD9467 HDL core. | | ||
- | | cf_ad9467.c | Implementation of the AD9467 HDL core access functions and ADC test and capture functions. | | ||
- | | spi.h | Header file for the Xilinx AXI SPI driver. | | ||
- | | spi.c | Implementation file for the Xilinx AXI SPI driver. | | ||
- | | main.c | Implementation of the program' | ||
- | ^ AD9467 Software Driver | ||
- | | AD9467.h | AD9467 software driver header file. | | ||
- | | AD9467.c | AD9467 software driver implementation file. | | ||
- | ^ AD9517 Software Driver | ||
- | | AD9517.h | AD9517 software driver header file. | | ||
- | | AD9517_cfg.h | AD9517 software driver configuration file. | | ||
- | | AD9517.c | AD9517 software driver implementation file. | | ||
- | ===== More information ===== | ||
<WRAP round help 80%> | <WRAP round help 80%> | ||
\\ | \\ | ||
[[ez> | [[ez> | ||
</ | </ |