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resources:fpga:xilinx:fmc:ad9250-fmc-250ebz [15 Mar 2013 18:51] – [Downloads] rejeesh kuttyresources:fpga:xilinx:fmc:ad9250-fmc-250ebz [11 Apr 2013 15:29] – [Downloads] rejeesh kutty
Line 183: Line 183:
 FPGA Referece Designs: FPGA Referece Designs:
 <WRAP round download 80%> <WRAP round download 80%>
-  * ** ML605 ** {{:resources:fpga:xilinx:fmc:cf_fmc176_ml605_edk_14_4_2013_03_15.tar.gz}} +  * ** ML605 ** {{:resources:fpga:xilinx:fmc:cf_fmc176_ml605_edk_14_4_2013_04_04.tar.gz}} 
-  * ** KC705 ** {{:resources:fpga:xilinx:fmc:cf_fmc176_kc705_edk_14_4_2013_03_15.tar.gz}} +  * ** KC705 ** {{:resources:fpga:xilinx:fmc:cf_fmc176_kc705_edk_14_4_2013_04_04.tar.gz}} 
-  * ** VC707 ** {{:resources:fpga:xilinx:fmc:cf_fmc176_vc707_edk_14_4_2013_03_15.tar.gz}} +  * ** VC707 ** {{:resources:fpga:xilinx:fmc:cf_fmc176_vc707_edk_14_4_2013_04_04.tar.gz}} 
-  * ** VC707 ** {{:resources:fpga:xilinx:fmc:cf_fmc176x2_vc707_edk_14_4_2013_03_15.tar.gz}} +  * ** VC707 ** {{:resources:fpga:xilinx:fmc:cf_fmc176x2_vc707_edk_14_4_2013_04_04.tar.gz}} 
-  * ** ZC706 ** {{:resources:fpga:xilinx:fmc:cf_fmc176_zc706_edk_14_4_2013_03_15.tar.gz}}+  * ** ZC706 ** {{:resources:fpga:xilinx:fmc:cf_fmc176_zc706_edk_14_4_2013_04_04.tar.gz}}
 </WRAP> </WRAP>
 +
 +Software Files:
 +<WRAP round download 80%>
 +  * ** ML605 ** {{:resources:fpga:xilinx:fmc:cf_fmc176_ml605_sw_14_4_2013_04_04.tar.gz}}
 +  * ** KC705 ** {{:resources:fpga:xilinx:fmc:cf_fmc176_kc705_sw_14_4_2013_04_04.tar.gz}}
 +  * ** VC707 ** {{:resources:fpga:xilinx:fmc:cf_fmc176_vc707_sw_14_4_2013_04_04.tar.gz}}
 +  * ** VC707 ** {{:resources:fpga:xilinx:fmc:cf_fmc176x2_vc707_sw_14_4_2013_04_04.tar.gz}}
 +  * ** ZC706 ** {{:resources:fpga:xilinx:fmc:cf_fmc176_zc706_sw_14_4_2013_04_04.tar.gz}}
 +</WRAP>
 +
  
 Only Xilinx coregen xco files are provided with the reference design. You must regenerate the IP core files using this file. See [[http://wiki.analog.com/resources/eval/user-guides/ad-fmcomms1-ebz/reference_hdl|generating Xilinx netlist/verilog files from xco files]] for details. Only Xilinx coregen xco files are provided with the reference design. You must regenerate the IP core files using this file. See [[http://wiki.analog.com/resources/eval/user-guides/ad-fmcomms1-ebz/reference_hdl|generating Xilinx netlist/verilog files from xco files]] for details.
resources/fpga/xilinx/fmc/ad9250-fmc-250ebz.txt · Last modified: 23 Apr 2013 23:23 by Robin Getz