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resources:fpga:xilinx:fmc:ad7961 [07 Aug 2013 14:32] – [Data Capture] Alexandru.Tofanresources:fpga:xilinx:fmc:ad7961 [25 Jan 2021 19:33] (current) – update renesas links after their web site update Robin Getz
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 ==== Running Demo (SDK) Program ==== ==== Running Demo (SDK) Program ====
  
-<WRAP round tip 80%>If you are not familiar with KC705 and/or Xilix tools, please visit\\ [[http://www.xilinx.com/products/boards-and-kits/EK-K7-KC705-G.htm]] for details.\\+<WRAP round tip 80%>If you are not familiar with KC705 and/or Xilix tools, please visit\\ [[xilinx>products/boards-and-kits/EK-K7-KC705-G.htm]] for details.\\
 </WRAP> </WRAP>
 Extract the project from the archive file to the location you desire.  Extract the project from the archive file to the location you desire. 
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 ==== FPGA Configuration ==== ==== FPGA Configuration ====
  
-Start IMPACT, and initialze the JTAG chain. The program should recognize the FPGA device. Program the device. +Start IMPACT, and initialze the JTAG chain. The program should recognize the FPGA device. Program the device using the ”../Bit/system.bit” file provided in the reference design archive.. 
  
 {{:resources:fpga:xilinx:fmc:cf_ad7961_impact.jpg?400|FPGA Programming}} {{:resources:fpga:xilinx:fmc:cf_ad7961_impact.jpg?400|FPGA Programming}}
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 ==== Data Capture ==== ==== Data Capture ====
  
-After successfully programming the FPGA, launch the "data_capture.bat" from the "../DataCapture" folder.+At this point everything is set up and it is possible to start the evaluation of the ADI hardware. To capture data from the ADC run the **data_capture.bat** script located in the **"../DataCapture"** folder from the reference design .zip file. Every time the script is run a new batch of 8192 samples are read from the ADC at the ADC's maximum sampling rate and saved into the Acquisition.csv file located in the same folder as the data capture script. On the UART terminal messages will be displayed to show the status of the program running on the FPGA as shown in the picture below.
  
-{{:resources:fpga:xilinx:fmc:cf_ad7961_datacapture.jpg?400|Data Capture}}+Data Capture Script\\ 
 +{{:resources:fpga:xilinx:fmc:cf_ad7961_datacapture.jpg?400|Data Capture}}\\
  
-After data has been read from the device, it will be stored in Acquisition.csv.+Acquisition.csv\\ 
 +{{:resources:fpga:xilinx:fmc:cf_ad7961_acquisition_file.jpg?400|Acquisition File}}\\ 
 + 
 +UART Messages\\ 
 +{{:resources:fpga:xilinx:interposer:teraterm_adc.png?400|UART messages}}\\ 
 + 
 +<WRAP round tip 80%>The first time the data capture script is run it is possible that an error will occur while the script is trying to connect to the system. Just run the script again and the error shouldn't appear anymore.</WRAP>
  
-{{:resources:fpga:xilinx:fmc:cf_ad7961_acquisition_file.jpg?400|Acquisition File}} 
  
 ===== Using the reference design ===== ===== Using the reference design =====
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 The reference design is built on a Microblaze based system. It consists of two functional modules, a LVDS interface, and a DMA interface. The LVDS interface captures and buffers data from the ADC. The data is captured using Echoed-Clock mode or Self-Clock mode (depending on the project). The DMA interface then transfers the samples to the external DDR-DRAM. The capture is initiated by the software, and transfered to the PC using a *.tcl script. The reference design is built on a Microblaze based system. It consists of two functional modules, a LVDS interface, and a DMA interface. The LVDS interface captures and buffers data from the ADC. The data is captured using Echoed-Clock mode or Self-Clock mode (depending on the project). The DMA interface then transfers the samples to the external DDR-DRAM. The capture is initiated by the software, and transfered to the PC using a *.tcl script.
  
-==== Registers ==== 
- 
-The IP Core contains only a control register, that sets/clears the EN pins of the device. 
  
 ===== Downloads ===== ===== Downloads =====
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 <WRAP round help 80%> <WRAP round help 80%>
-  * Questions? [[http://ez.analog.com/post!input.jspa?containerType=14&container=2061|Ask Help & Support]].+  * Questions? [[ez>fpga|Ask Help & Support]].
 </WRAP> </WRAP>
  
 ===== Zip file contents ===== ===== Zip file contents =====
  
-The zip file contains, in most cases, the following files and/or directories. To rebuild the reference design simply double click the XMP file and run the tool. To build SDK, select a workspace and use the C file to build the elf file. Please refer to [[http://www.xilinx.com/support/documentation/dt_edk_edk13-2.htm|Xilinx EDK documentation]] for details.+The zip file contains, in most cases, the following files and/or directories. To rebuild the reference design simply double click the XMP file and run the tool. To build SDK, select a workspace and use the C file to build the elf file. Please refer to [[xilinx>support/documentation/dt_edk_edk13-2.htm|Xilinx EDK documentation]] for details.
  
 | Bit   | The bitfile required for Quick Evaluation | | Bit   | The bitfile required for Quick Evaluation |
resources/fpga/xilinx/fmc/ad7961.txt · Last modified: 25 Jan 2021 19:33 by Robin Getz

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