The AD7960 is an 18-bit, 5 MSPS charge redistribution successive approximation (SAR), analog-to-digital converter (ADC). The SAR architecture allows unmatched performance both in noise and in linearity. The AD7960 contains a low power, high speed, 18-bit sampling ADC, an internal conversion clock and an internal reference buffer. On the CNV± edge, the AD7960 samples the voltage difference between the IN+ and IN- pins. The voltages on these pins swing in opposite phase between 0 V and 4.096 V/5 V. The reference voltage is applied to the part externally. All conversion results are available on a single LVDS self-clocked or echo-clocked serial interface.
The reference design has been tested with KC705. It should be easily portable to other boards such as ML605 and VC707, only the UCF and MHS files need to be changed. The bit file provided combines the FPGA bit file and the SDK elf files. It may be used for a quick check on the system. All you need is the hardware and the programmer (IMPACT). This bit file configuration also captures 8192 samples from the ADC and saves them in a *.csv file.
If you are not familiar with KC705 and/or Xilix tools, please visit
products/boards-and-kits/EK-K7-KC705-G.htm for details.
Extract the project from the archive file to the location you desire.
To begin, connect the EVAL-AD7960FMCZ board to the FMC-HPC or FMC-LPC connector (depending on archive file) of KC705 board (see images below). Connect power and USB cable from the PC to the JTAG USB connectors on the edge of the KC705. Connect a signal source to the AIN+(J5) and AIN-(J4) SMA connectors of the FMC card. After the hardware setup, turn the power on to the KC705.
Start IMPACT, and initialze the JTAG chain. The program should recognize the FPGA device. Program the device using the ”../Bit/system.bit” file provided in the reference design archive..
At this point everything is set up and it is possible to start the evaluation of the ADI hardware. To capture data from the ADC run the data_capture.bat script located in the “../DataCapture” folder from the reference design .zip file. Every time the script is run a new batch of 8192 samples are read from the ADC at the ADC's maximum sampling rate and saved into the Acquisition.csv file located in the same folder as the data capture script. On the UART terminal messages will be displayed to show the status of the program running on the FPGA as shown in the picture below.
The first time the data capture script is run it is possible that an error will occur while the script is trying to connect to the system. Just run the script again and the error shouldn't appear anymore.
The reference design is built on a Microblaze based system. It consists of two functional modules, a LVDS interface, and a DMA interface. The LVDS interface captures and buffers data from the ADC. The data is captured using Echoed-Clock mode or Self-Clock mode (depending on the project). The DMA interface then transfers the samples to the external DDR-DRAM. The capture is initiated by the software, and transfered to the PC using a *.tcl script.
FPGA Referece Designs:
The zip file contains, in most cases, the following files and/or directories. To rebuild the reference design simply double click the XMP file and run the tool. To build SDK, select a workspace and use the C file to build the elf file. Please refer to Xilinx EDK documentation for details.
|The bitfile required for Quick Evaluation
|Data Capture script
|Verilog file used to interface the component to a FPGA.
|The XPS Project.
|C files and headers