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resources:fpga:xilinx:fmc:ad-fmcjesdadc1-ebz [20 Nov 2019 10:36] – Fix a grammar mistake Stanca-Florina Popresources:fpga:xilinx:fmc:ad-fmcjesdadc1-ebz [22 Nov 2019 14:11] – Update block diagrams and description of the reference design Stanca-Florina Pop
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 ===== Using the reference design ===== ===== Using the reference design =====
  
-The reference design is built on a microblaze based system parameterized for linux. A functional block diagram of the design is given below. The reference design contains both ADC and DAC pcores. If you are using the AD-FMCJESDADC1-EBZ, you can ignore the DAC pcores.+The reference design is built on a microblaze based system parameterized for linux. A functional block diagram of the design is given below. 
  
-{{:resources:fpga:xilinx:fmc:cf_fmc27x_bd.jpg?400|block diagram}}+=== Xilinx block diagram === 
 +{{:resources:fpga:xilinx:fmc:ad-fmcjesdadc1-ebz:fmcjesdadc1_xilinx.svg?800|block diagram}}
  
-The reference design consists of two identical instances of pcores for the DAC. On the ADC side, it consists of a single JESD204B core and two identical instances of AD9250 pcores.+=== AD-FMCJESDADC1-EBZ block diagram === 
 +{{:resources:fpga:xilinx:fmc:ad-fmcjesdadc1-ebz:ad-fmcjesdadc1-ebz.svg?700|block diagram}}
  
-The AD9129 core consists of three functional modules, the DAC interface, a DDS (using Xilinx IP) and a VDMA interface. The frequency of DDS may be set via the programming interface. Alternatively a custom data sequence may be used via the VDMA interface.+The reference design consists of a single JESD204B core and two identical instances of AD9250 pcores.
  
 The AD9250 core consists of three functional modules, the ADC interface, a PN9/PN23 monitor and a DMA interface.  The ADC interface captures and buffers data from the JESD204B core. The DMA interface then transfers the samples to the external DDR-DRAM. The capture is initiated by the software. The status of capture (overflow, over the range) are reported back to the software. The AD9250 core consists of three functional modules, the ADC interface, a PN9/PN23 monitor and a DMA interface.  The ADC interface captures and buffers data from the JESD204B core. The DMA interface then transfers the samples to the external DDR-DRAM. The capture is initiated by the software. The status of capture (overflow, over the range) are reported back to the software.
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 | [[http://www.4dsp.com/FMC176.php|FMC-176]] | 4 (2 x AD9250) | 2 (2 x AD9129) | | [[http://www.4dsp.com/FMC176.php|FMC-176]] | 4 (2 x AD9250) | 2 (2 x AD9129) |
 | [[http://www.4dsp.com/FMC230.php|FMC-230]] |  | 2 (2 x AD9129) | | [[http://www.4dsp.com/FMC230.php|FMC-230]] |  | 2 (2 x AD9129) |
-| [[adi>AD9250#product-samples|AD-FMCJESDADC1-EBZ]] | 4 (2 x AD9250) | |+| [[adi>AD-FMCJESDADC1-EBZ#product-samples|AD-FMCJESDADC1-EBZ]] | 4 (2 x AD9250) | |
  
  
resources/fpga/xilinx/fmc/ad-fmcjesdadc1-ebz.txt · Last modified: 20 Dec 2023 12:00 by Stefan-Robert Raus

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