This version is outdated by a newer approved version.
This version (25 Feb 2016 14:24) was approved by Mihai Ionut Suciu.The Previously approved version (28 Aug 2015 09:15) is available.
This version (25 Feb 2016 14:24) was approved by Mihai Ionut Suciu.The Previously approved version (28 Aug 2015 09:15) is available.This is an old revision of the document!
Table of Contents
ADI AD-FMCADC4-EBZ Boards & Xilinx Reference Design
Introduction
This design uses the Xilinx JESD204B core which requires either a commercial (pay $) or evaluation license (eventually pay $) to use. If this is not what you are looking for, you should not use this board.
The AD-FMCADC4-EBZ is a high speed 4 channel data acquisition board featuring two AD9680 dual channel ADC at 1000 MSPS and four ADA4961 ADA4961 low distortion, 3.2 GHz, RF DGA driving each converter. The FMC form factor supports the JESD204B high speed serial interface. All clocking and channel synchronization is support on-board using the AD9528 AD9528 clock generator. This board meets most of the FMC specifications in terms of mechanical size, mounting hole locations, and more. For that information, please refer to the FMC specification. Although this board does meet most of the FMC specifications, it is not meant as a commercial off the shelf (COTS) board. If a commercial, ready to go integrate product is required, please refer to one of the many FMC manufacturers. This board is targeted for the use of ADI reference designs that work with Xilinx development systems. ADI provides a complete source (HDL and software) to re-create these projects (minus the IP provided by the FPGA vendors).
The reference design includes the device data capture via the JESD204B serial interface and the SPI interface. The samples are written to the external DDR-DRAM. It allows programming the device and monitoring it's internal registers via SPI.
Supported Devices
Supported Carriers
- ZC706 HPC Slot
Required Software
- We're upgrade the Xilinx tools on every release. The supported version number can be found in our git repository .
- A UART terminal (Tera Term/Hyperterminal), baud rate 115200.
Downloads
The HDL Reference Designs and the no-OS Software can be downloaded from the Analog Devices github.
HDL Source
- ZC706 HDL Reference design: https://github.com/analogdevicesinc/hdl/tree/master/projects/fmcadc4/zc706
resources/fpga/xilinx/fmc/ad-fmcadc4-ebz.1456406674.txt.gz · Last modified: 25 Feb 2016 14:24 by Mihai Ionut Suciu