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| resources:fpga:xilinx:fmc:ad-fmcadc4-ebz [28 Jun 2017 13:57] – Typo fix Dragos Bogdan | resources:fpga:xilinx:fmc:ad-fmcadc4-ebz [03 Jan 2021 22:12] (current) – fix links Robin Getz |
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| ====== ADI AD-FMCADC4-EBZ Boards & Xilinx Reference Design ====== | ====== ADI AD-FMCADC4-EBZ Boards & Xilinx Reference Design (OBSOLETE) ====== |
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| ===== Introduction ===== | ===== Introduction ===== |
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| <WRAP important round>This design uses the [[http://www.xilinx.com/products/intellectual-property/EF-DI-JESD204.htm|Xilinx JESD204B core]] which requires either a commercial (pay $) or [[http://www.xilinx.com/ipcenter/ipevaluation/jesd204_evaluation.htm|evaluation]] license (eventually pay $) to use. If this is not what you are looking for, you should not use this board.</WRAP> | <WRAP round important 65%> |
| | Support for AD-FMCADC4-EBZ project on this website only for legacy purposes. The support for this project has been discontinued, latest tested release being 2018_r2. |
| | </WRAP> |
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| The [[adi>EVAL-AD-FMCADC4-EBZ|AD-FMCADC4-EBZ]] is a high speed 4 channel data acquisition board featuring two [[adi>AD9680]] dual channel ADC at 1000 MSPS and four ADA4961 [[adi>ADA4961]] low distortion, 3.2 GHz, RF DGA driving each converter. The FMC form factor supports the JESD204B high speed serial interface. All clocking and channel synchronization is support on-board using the AD9528 [[adi>AD9528]] clock generator. This board meets most of the FMC specifications in terms of mechanical size, mounting hole locations, and more. For that information, please refer to the FMC specification. | The [[adi>EVAL-AD-FMCADC4-EBZ|AD-FMCADC4-EBZ]] is a high speed 4 channel data acquisition board featuring two [[adi>AD9680]] dual channel ADC at 1000 MSPS and four ADA4961 [[adi>ADA4961]] low distortion, 3.2 GHz, RF DGA driving each converter. The FMC form factor supports the JESD204B high speed serial interface. All clocking and channel synchronization is support on-board using the AD9528 [[adi>AD9528]] clock generator. This board meets most of the FMC specifications in terms of mechanical size, mounting hole locations, and more. For that information, please refer to the FMC specification. |
| ===== Supported Devices ===== | ===== Supported Devices ===== |
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| * [[http://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/EVAL-AD-FMCADC4-EBZ.html#eb-overview|AD-FMCADC4-EBZ]] | * [[adi>en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/EVAL-AD-FMCADC4-EBZ.html#eb-overview|AD-FMCADC4-EBZ]] |
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| ===== Supported Carriers ===== | ===== Supported Carriers ===== |
| ===== Required Software ===== | ===== Required Software ===== |
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| * We're upgrade the Xilinx tools on every release. The supported version number can be found in our [[https://github.com/analogdevicesinc/hdl/tree/master | git repository ]]. | * We're upgrade the Xilinx tools on every release. The supported version number can be found in our [[https://github.com/analogdevicesinc/hdl/blob/hdl_2018_r2/projects/scripts/adi_project.tcl#L10 | git repository ]]. |
| * A UART terminal (Tera Term/Hyperterminal), baud rate 115200. | * A UART terminal (Tera Term/Hyperterminal), baud rate 115200. |
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| ===== HDL Source ===== | ===== HDL Source ===== |
| <WRAP center round download> | <WRAP center round download> |
| * ZC706 HDL Reference design: [[https://github.com/analogdevicesinc/hdl/tree/master/projects/fmcadc4/zc706]] | * ZC706 HDL Reference design: [[https://github.com/analogdevicesinc/hdl/tree/hdl_2018_r2/projects/fmcadc4/zc706]] |
| </WRAP> | </WRAP> |
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| ===== No-OS Software Source ===== | ===== No-OS Software Source ===== |
| <WRAP center round download> | <WRAP center round download> |
| * AD-FMCADC4-EBZ No-OS - https://github.com/analogdevicesinc/no-OS/tree/master/ad-fmcadc4-ebz | * AD-FMCADC4-EBZ No-OS - https://github.com/analogdevicesinc/no-OS/tree/2018_R2/fmcadc4 |
| </WRAP> | </WRAP> |
