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| resources:fpga:peripherals:spi_engine [30 Mar 2015 14:40] – [Interfaces] Lars-Peter Clausen | resources:fpga:peripherals:spi_engine [22 Dec 2022 13:07] (current) – remove broken backlinks sergiu arpadi |
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| The core component of the SPI Engine framework is a lean but powerful fully programmable execution module, which implements the SPI bus control logic. The SPI Engine execution module is controlled by a command stream which is generated by a separate module. Different command stream master modules are available and can be used depending on the system requirements. For example a software controlled memory mapped command stream offers high flexibility, while a offload core which executes a pre-programmed command stream when triggered by an external event allows for very low latency response times. By using a SPI Engine interconnect it is possible to connect multiple command stream master modules to a SPI Engine execution module. | The core component of the SPI Engine framework is a lean but powerful fully programmable execution module, which implements the SPI bus control logic. The SPI Engine execution module is controlled by a command stream which is generated by a separate module. Different command stream master modules are available and can be used depending on the system requirements. For example a software controlled memory mapped command stream offers high flexibility, while a offload core which executes a pre-programmed command stream when triggered by an external event allows for very low latency response times. By using a SPI Engine interconnect it is possible to connect multiple command stream master modules to a SPI Engine execution module. |
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| ==== Sub-modules ==== | |
| | ===== Sub-modules ===== |
| |
| * [[.:spi_engine:engine|Execution Module]]: Main module which processes a SPI engine command stream and implements the SPI bus interface logic | * [[.:spi_engine:engine|Execution Module]]: Main module which processes a SPI engine command stream and implements the SPI bus interface logic |
| * [[.:spi_engine:axi|AXI Interface Module]]: Memory mapped software accessible interface to a SPI Engine command stream and/or offload cores | * [[.:spi_engine:axi|AXI Interface Module]]: Memory mapped software accessible interface to a SPI Engine command stream and/or offload cores |
| * [[.:spi_engine:offload|Offload Module]]: Stores a SPI Engine command stream, execution is triggered by an external event | * [[.:spi_engine:offload|Offload Module]]: Stores a SPI Engine command stream, execution is triggered by an external event |
| * [[.:spi_engine:xbar|Interconnect Module]]: Connects multiple SPI Engine command streams to a SPI Engine execution module | * [[.:spi_engine:interconnect|Interconnect Module]]: Connects multiple SPI Engine command streams to a SPI Engine execution module |
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| ==== Interfaces ==== | |
| | ===== Interfaces ===== |
| |
| * [[.:spi_engine:spi_engine_control_interface|SPI Engine Control Interface]]: SPI Engine command stream | * [[.:spi_engine:spi_engine_control_interface|SPI Engine Control Interface]]: SPI Engine command stream |
| * [[.:spi_engine:spi_bus_interface|SPI Bus Interface]]: Low-level SPI bus interface | * [[.:spi_engine:spi_bus_interface|SPI Bus Interface]]: Low-level SPI bus interface |
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| ==== Software ==== | |
| |
| * [[Linux Driver]]: Linux driver for the SPI Engine framework | ===== Software ===== |
| * [[No-OS bare-metal Driver]]: No-OS bare-metal driver | |
| * [[SPI Engine Compiler]]: Compiler for generating SPI Engine bytecode | |
| * [[.:spi_engine:instruction_format|SPI Engine Instruction Format]]: Overview of the SPI Engine Instruction format | |
| |
| ==== Tutorial ==== | * [[resources:tools-software:linux-drivers:spi:spi_engine|Linux Driver]]: Linux driver for the SPI Engine framework |
| | * [[.:spi_engine:instruction_format|SPI Engine Instruction Format]]: Overview of the SPI Engine Instruction format |
| |
| ==== Related IP Cores ==== | |
| | ===== Related IP Cores ===== |
| |
| This list contains cores that are not part of the core SPI engine framework but make use of its interfaces and are intend to be used together with the SPI engine framework. | This list contains cores that are not part of the core SPI engine framework but make use of its interfaces and are intend to be used together with the SPI engine framework. |
| * [[util_sigma_delta_spi|Sigma-Delta SPI Util]]: Helper module for interfacing ADCs from the Analog Devices Sigma-Delta family | * [[util_sigma_delta_spi|Sigma-Delta SPI Util]]: Helper module for interfacing ADCs from the Analog Devices Sigma-Delta family |
| |
| ==== Examples ==== | |
| |
| * CN0363 - Colorimeter application using the [[adi>AD7175-2]] Sigma-Delta ADC | ===== Examples ===== |
| | |
| | * [[resources:eval:user-guides:eval-cn0363-pmdz|CN0363]] - Colorimeter application using the [[adi>AD7175-2]] Sigma-Delta ADC |
| | * [[resources:eval:user-guides:adaq7980-sdz]] - A 16-bit ADC subsystem with four common signal processing and conditioning blocks. |
| | * [[resources:tools-software:uc-drivers:ad5766]] - 16-channel, 16-/12-bit, voltage output Digital-to-Analog Converters (DAC) |
| | * [[resources:eval:user-guides:ad7768-1]] - The AD7768-1 is a low power, high performance, Σ-Δ analog-to-digital converter (ADC). |
| | * [[https://github.com/analogdevicesinc/hdl/tree/master/projects/ad40xx_fmc|AD40xx-FMC]] - Evaluation Board for the AD4000 Series 16-/18-/20-Bit Precision SAR ADCs |
| | * [[:resources:eval:user-guides:ad469x|AD469x]] - 16-Bit, 16-Channel, 500 kSPS/1 MSPS, Easy Drive Multiplexed SAR ADC |
| | * [[:resources:eval:user-guides:ad463x:hdl|AD4630-24 / AD4030-24 / AD4630-16]] - 16/24-Bit, 2 MSPS Single or Dual Channel SAR ADC |
| | |
| | ===== Additional Resources ===== |
| | |
| | * {{:resources:fpga:peripherals:spi-engine3.pdf|Presentation: SPI Engine Design Philosophy}} |
| | * [[:resources:fpga:peripherals:spi_engine:tutorial|PulSAR ADC Tutorial]] |
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