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resources:fpga:peripherals:spi_engine [09 Feb 2021 18:23] – [Examples] Fix broken link Istvan Csomortani | resources:fpga:peripherals:spi_engine [13 Oct 2021 08:45] – Edit footer Iulia Moldovan | ||
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The core component of the SPI Engine framework is a lean but powerful fully programmable execution module, which implements the SPI bus control logic. The SPI Engine execution module is controlled by a command stream which is generated by a separate module. Different command stream master modules are available and can be used depending on the system requirements. For example a software controlled memory mapped command stream offers high flexibility, | The core component of the SPI Engine framework is a lean but powerful fully programmable execution module, which implements the SPI bus control logic. The SPI Engine execution module is controlled by a command stream which is generated by a separate module. Different command stream master modules are available and can be used depending on the system requirements. For example a software controlled memory mapped command stream offers high flexibility, | ||
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===== Sub-modules ===== | ===== Sub-modules ===== | ||
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===== Interfaces ===== | ===== Interfaces ===== | ||
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===== Software ===== | ===== Software ===== | ||
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* [[util_sigma_delta_spi|Sigma-Delta SPI Util]]: Helper module for interfacing ADCs from the Analog Devices Sigma-Delta family | * [[util_sigma_delta_spi|Sigma-Delta SPI Util]]: Helper module for interfacing ADCs from the Analog Devices Sigma-Delta family | ||
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===== Examples ===== | ===== Examples ===== | ||
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* [[resources: | * [[resources: | ||
* [[https:// | * [[https:// | ||
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===== Additional Documents ===== | ===== Additional Documents ===== | ||
* {{: | * {{: | ||
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+ | {{navigation HDL User Guide# |