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resources:fpga:peripherals:spi_engine:spi_bus_interface [30 Mar 2015 17:42] – [SPI Bus Interface] Lars-Peter Clausenresources:fpga:peripherals:spi_engine:spi_bus_interface [11 May 2018 17:42] (current) – [Files] Switch to master branch Istvan Csomortani
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 The SPI bus interface carries logical low-level SPI bus signals. The SPI bus interface carries logical low-level SPI bus signals.
  
 +===== Files =====
 +
 +^ Name ^ Description ^
 +| [[github>hdl?master/library/spi_engine/interfaces/spi_master_rtl.xml|spi_master_rtl.xml]] | Interface definition file |
 ===== Signal Pins ===== ===== Signal Pins =====
  
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 | ''sdo'' | Output | SPI SDO (MOSI) signal. | | ''sdo'' | Output | SPI SDO (MOSI) signal. |
 | ''sdo_t'' | Output | ''sdo'' tri-state enable. If 1 the MOSI signal should be tristated and not be connected to ''sdo''  | | ''sdo_t'' | Output | ''sdo'' tri-state enable. If 1 the MOSI signal should be tristated and not be connected to ''sdo''  |
-| ''sdi'' | Input | SPI SDI (MISO) signal. |+| ''sdi'' | Input | SPI SDI (MISO) signal. Execution module supports max 8 individual ''sdi'' lines. |
 | ''cs'' | Output | SPI chip-select signal. | | ''cs'' | Output | SPI chip-select signal. |
 | ''three_wire'' | Output | If set to 1 the bus should operate in three-wire mode. In three-wire mode ''sdi'' is connected to MOSI instead of MISO. | | ''three_wire'' | Output | If set to 1 the bus should operate in three-wire mode. In three-wire mode ''sdi'' is connected to MOSI instead of MISO. |
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 In some configurations three-wire support may not be required and ''sdi'' can directly be connected to the input buffer for the ''miso'' signal. Similarly when ''mosi'' tri-stating is not required the ''sdo'' signal can be directly connected to the ''mosi'' signal leaving the ''sdo_t'' signal unconnected. In some configurations three-wire support may not be required and ''sdi'' can directly be connected to the input buffer for the ''miso'' signal. Similarly when ''mosi'' tri-stating is not required the ''sdo'' signal can be directly connected to the ''mosi'' signal leaving the ''sdo_t'' signal unconnected.
 +
 +==== Example Verilog IO configuration ====
 +
 +The following example Verilog code shows the most generic IO configuration, which represents the diagram above. Depending on system requirements some simplification might be possible.
 +
 +Signals with **phy** prefix are assumed to be connected to the physical input/output pins and signals with the **spi** prefix are assumed to be connected SPI-Engine bus interface.
 +
 +<code verilog>
 +assign phy_sclk = spi_sclk;
 +assign phy_cs = spi_cs;
 +assign phy_mosi = spi_sdo_t ? 1'bz : spi_sdo;
 +assign spi_sdi = spi_three_wire ? phy_mosi : phy_miso;
 +</code>
  
  
 ===== More Information ===== ===== More Information =====
   * [[.|SPI Engine Framework]]   * [[.|SPI Engine Framework]]
resources/fpga/peripherals/spi_engine/spi_bus_interface.1427730131.txt.gz · Last modified: 30 Mar 2015 17:42 by Lars-Peter Clausen

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