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resources:fpga:peripherals:spi_engine:spi_bus_interface [30 Mar 2015 11:48] – Lars-Peter Clausen | resources:fpga:peripherals:spi_engine:spi_bus_interface [11 May 2018 17:42] (current) – [Files] Switch to master branch Istvan Csomortani | ||
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====== SPI Bus Interface ====== | ====== SPI Bus Interface ====== | ||
+ | The SPI bus interface carries logical low-level SPI bus signals. | ||
+ | |||
+ | ===== Files ===== | ||
+ | |||
+ | ^ Name ^ Description ^ | ||
+ | | [[github> | ||
===== Signal Pins ===== | ===== Signal Pins ===== | ||
^ Name ^ Direction (Master) ^ Description ^ | ^ Name ^ Direction (Master) ^ Description ^ | ||
- | | sclk | Output | SPI Clock | | + | | '' |
- | | sdo | Output | | | + | | '' |
- | | sdo_t | Output | | | + | | '' |
- | | sdi | Input | | | + | | '' |
- | | cs | Output | Chip-select signal | | + | | '' |
- | | three_wire | Output | | | + | | '' |
+ | |||
+ | ===== IO configuration ===== | ||
+ | |||
+ | {{ : | ||
+ | |||
+ | The SPI bus interface only carries a logical representation of the low-level SPI bus signals. The top-level module in the FPGA design project is responsible for translating the signal to physical SPI bus signals by instantiating and connecting it to appropriate IO primitives. | ||
+ | |||
+ | The '' | ||
+ | |||
+ | In some configurations three-wire support may not be required and '' | ||
+ | |||
+ | ==== Example Verilog IO configuration ==== | ||
+ | |||
+ | The following example Verilog code shows the most generic IO configuration, | ||
+ | |||
+ | Signals with **phy** prefix are assumed to be connected to the physical input/ | ||
+ | |||
+ | <code verilog> | ||
+ | assign phy_sclk = spi_sclk; | ||
+ | assign phy_cs = spi_cs; | ||
+ | assign phy_mosi = spi_sdo_t ? 1'bz : spi_sdo; | ||
+ | assign spi_sdi = spi_three_wire ? phy_mosi : phy_miso; | ||
+ | </ | ||
===== More Information ===== | ===== More Information ===== | ||
* [[.|SPI Engine Framework]] | * [[.|SPI Engine Framework]] |