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resources:fpga:peripherals:spi_engine:interconnect [26 May 2015 18:57] – [Files] Lars-Peter Clausenresources:fpga:peripherals:spi_engine:interconnect [11 May 2018 17:47] – [Files] Switch to master Istvan Csomortani
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 ^ Name ^ Description ^ ^ Name ^ Description ^
-| [[github>hdl?dev/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v|spi_engine_interconnect.v]] | Verilog source for the peripheral. | +| [[github>hdl?master/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v|spi_engine_interconnect.v]] | Verilog source for the peripheral. | 
-| [[github>hdl?dev/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect_ip.tcl|spi_engine_interconnect_ip.tcl]] | TCL script to generate the Vivado IP-integrator project for the peripheral. |+| [[github>hdl?master/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect_ip.tcl|spi_engine_interconnect_ip.tcl]] | TCL script to generate the Vivado IP-integrator project for the peripheral. |
  
 ===== Configuration Parameters ===== ===== Configuration Parameters =====
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 ===== Theory of Operation ===== ===== Theory of Operation =====
  
-The SPI Engine Interconnect module has multiple [[SPI Engine Control Interface]] slave ports and a single [[SPI Engine Control Interface]] master port. It can be used to connect multiple command stream generators to a single command execution engine. Arbitration between the streams is done on a priority basis, streams with a lower index have higher priority. This means if commands are present on two streams arbitration will be granted to the one with the lower index. Once arbitration has been granted the port it was granted to stays in control until it sends a SYNC command. When the interconnect module sees a SYNC command arbitration will re-evaluated after the SYNC command has been completed. This makes sure that once a SPI transaction consisting of multiple commands has been started it is able to complete without being interrupted by a higher priority stream.+The SPI Engine Interconnect module has multiple [[SPI Engine Control Interface]] slave ports and a single [[SPI Engine Control Interface]] master port. It can be used to connect multiple command stream generators to a single command execution engine. Arbitration between the streams is done on a priority basis, streams with a lower index have higher priority. This means if commands are present on two streams arbitration will be granted to the one with the lower index. Once arbitration has been granted the port it was granted to stays in control until it sends a SYNC command. When the interconnect module sees a SYNC command arbitration will be re-evaluated after the SYNC command has been completed. This makes sure that once a SPI transaction consisting of multiple commands has been started it is able to complete without being interrupted by a higher priority stream.
  
 ===== More Information ===== ===== More Information =====
   * [[.|SPI Engine Framework]]   * [[.|SPI Engine Framework]]
resources/fpga/peripherals/spi_engine/interconnect.txt · Last modified: 04 Sep 2019 12:47 by Istvan Csomortani

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