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resources:fpga:peripherals:spi_engine:interconnect [11 May 2018 17:47] – [Files] Switch to master Istvan Csomortani | resources:fpga:peripherals:spi_engine:interconnect [04 Sep 2019 12:47] (current) – Add configuration parameters, fix some grammar mistakes Istvan Csomortani | ||
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{{ : | {{ : | ||
- | The SPI Engine Interconnect module allows | + | The SPI Engine Interconnect module allows |
- | Combining multiple command stream generators in a design and connecting them to a single execution | + | Combining multiple command stream generators in a design and connecting them to a single execution |
===== Files ===== | ===== Files ===== | ||
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^ Name ^ Description ^ Default ^ | ^ Name ^ Description ^ Default ^ | ||
+ | | '' | ||
+ | | '' | ||
===== Signal and Interface Pins ===== | ===== Signal and Interface Pins ===== | ||
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^ Name ^ Type ^ Description ^ | ^ Name ^ Type ^ Description ^ | ||
| clk | Clock | A signals of the module are synchronous to this clock. | | | clk | Clock | A signals of the module are synchronous to this clock. | | ||
- | | resetn | Synchronous active low reset | Resets the internal state of the module. | | + | | resetn | Synchronous active-low reset | Resets the internal state of the module. | |
| s0_ctrl | [[SPI Engine Control Interface]] slave | Connects to the first control interface master | | | s0_ctrl | [[SPI Engine Control Interface]] slave | Connects to the first control interface master | | ||
| s1_ctrl | [[SPI Engine Control Interface]] slave | Connects to the second control interface master | | | s1_ctrl | [[SPI Engine Control Interface]] slave | Connects to the second control interface master | |