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resources:fpga:peripherals:spi_engine:axi [04 Sep 2019 12:42] – Update the links to the source code Istvan Csomortaniresources:fpga:peripherals:spi_engine:axi [03 Dec 2019 14:52] – Add SPI Engine register map and Access type table Stanca-Florina Pop
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 ===== Register Map ===== ===== Register Map =====
  
-^ Address ^ Name ^ Type ^ Reset Value ^ Description ^ +{{page>:resources:fpga:docs:hdl:regmap##SPI Engine (axi_spi_engine)&nofooter&noeditbtn}} 
-| 0x00 | VERSION | R | + 
-| [31:0] | VERSION | R |0x00010071 | Version of the peripheral. Follows the [[ADI semantic versioning]]. | +|< 100% 10em 10em >| 
-| 0x04 | PERIPHERAL_ID | R | 0x00000000 | In case of multiple instances, each instance will have a unique ID| +^ Access Type ^ Name ^ Description ^ 
-| 0x08 | SCRATCH | RW | 0x00000000 | Scratch register. | +| RO | Read-only | Reads will return the current register value. Writes have no effect. | 
-| 0x0C | DATA_WIDTH | R | 0x00000008 | Data width of the SDI/SDO parallel interface. Is equal with the maximum supported transfer length in bits.| +| RW | Read-write | Reads will return the current register value. Writes will change the current register value. | 
-| 0x40 | ENABLE | RW| 0x00000000 | Enable register. If the enable bit is set to 0 the internal state of the peripheral is reset. For proper operation, the bit needs to be set to 1. | +| WO | Write-only | Writes will change the current register value. Reads have no effect. | 
-| 0x80 | IRQ_MASK | RW | 0x00000000 | IRQ mask | +| RW1C | Write-1-to-clear | Reads will return the current register value. Writing the register will clear those bits of the register which were set to 1 in the value written. Bits are set by hardware. | 
-| [0] | CMD_ALMOST_EMPTY | RW | 0 | If set to 0 the CMD_ALMOST_EMPTY interrupt is masked. | +
-| [1] | SDO_ALMOST_EMPTY | RW | 0 | If set to 0 the SDO_ALMOST_EMPTY interrupt is masked. | +
-| [2] | SDI_ALMOST_FULL | RW | 0 | If set to 0 the SDI_ALMOST_FULL interrupt is masked. | +
-| [3] | SYNC_EVENT | RW | 0 | If set to 0 the SYNC_EVENT interrupt is masked. | +
-| 0x84 | IRQ_PENDING | W1C |0x00000000 | Pending IRQs with mask | +
-| 0x88 | IRQ_SOURCE | W1C |0x00000000 | Pending IRQs without mask | +
-| 0xc0 | SYNC_ID | R | 0x00000000 | Last synchronization event ID received from the SPI engine control interface. | +
-| 0xd0 | CMD_FIFO_ROOM | R | 0x???????? ((The reset value of the CMD_FIFO_ROOM register depends on the setting of the CMD_FIFO_ADDRESS_WIDTH parameter)) | Number of free entries in the command FIFO. | +
-| 0xd4 | SDO_FIFO_ROOM | R | 0x???????? ((The reset value of the SDO_FIFO_ROOM register depends on the setting of the SDO_FIFO_ADDRESS_WIDTH parameter)) | Number of free entries in the serial-data-out FIFO. | +
-| 0xd8 | SDI_FIFO_LEVEL | R | 0x00000000 | Number of valid entries in the serial-data-in FIFO. | +
-| 0xe0 | CMD_FIFO | W | 0x????????? | Command FIFO register. Writing to this register inserts an entry into the command FIFO. Writing to this register when the command FIFO is full has no effect and the written entry is discarded. Reading from this register always returns 0x00000000. | +
-| 0xe4 | SDO_FIFO | W | 0x????????? | SDO FIFO register. Writing to this register inserts an entry into the SDO FIFO. Writing to this register when the SDO FIFO is full has no effect and the written entry is discarded. Reading from this register always returns 0x00000000. | +
-| 0xe8 | SDI_FIFO | R | 0x????????? | SDI FIFO register. Reading from this register removes the first entry from the SDI FIFO. Reading this register when the SDI FIFO is empty will return undefined data. Writing to it has no effect. | +
-| 0xf0 | SDI_FIFO_PEEK | R| 0x???????? | SDI FIFO peek register. Reading from this register returns the first entry from the SDI FIFO, but without removing it from the FIFO. Reading this register when the SDI FIFO is empty will return undefined data. Writing to it has no effect. | +
-| 0x100 | OFFLOAD0_EN | RW | 0 | Set this bit to enable the offload module. | +
-| 0x108 | OFFLOAD0_MEM_RESET | RW | 0 | Reset the memory of the offload module. | +
-| 0x110 | OFFLOAD0_CDM_FIFO | W | 0x???????? | Offload command FIFO register. Writing to this register inserts an entry into the command FIFO of the offload module. Writing to this register when the command FIFO is full has no effect and the written entry is discarded. Reading from this register always returns 0x00000000. | +
-| 0x114 | OFFLOAD0_SDO_FIFO | W | 0x???????? | Offload SDO FIFO register. Writing to this register inserts an entry into the offload SDO FIFO. Writing to this register when the SDO FIFO is full has no effect and the written entry is discarded. Reading from this register always returns 0x00000000. |+
  
 ===== Theory of Operation ===== ===== Theory of Operation =====
resources/fpga/peripherals/spi_engine/axi.txt · Last modified: 13 Oct 2021 10:10 by Iulia Moldovan

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