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resources:fpga:peripherals:spi_engine:axi [04 Sep 2019 12:39] – Add offload CMD and SDO fifo registers Istvan Csomortani | resources:fpga:peripherals:spi_engine:axi [03 Dec 2019 14:52] – Add SPI Engine register map and Access type table Stanca-Florina Pop | ||
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^ Name ^ Description ^ | ^ Name ^ Description ^ | ||
- | | [[github> | + | | [[github> |
- | | [[github> | + | | [[github> |
===== Configuration Parameters ===== | ===== Configuration Parameters ===== | ||
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===== Register Map ===== | ===== Register Map ===== | ||
- | ^ Address | + | {{page>: |
- | | 0x00 | VERSION | + | |
- | | [31:0] | VERSION | R |0x00010071 | Version of the peripheral. Follows the [[ADI semantic versioning]]. | | + | |< 100% 10em 10em >| |
- | | 0x04 | PERIPHERAL_ID | R | 0x00000000 | In case of multiple instances, each instance | + | ^ Access Type ^ Name ^ Description ^ |
- | | 0x08 | SCRATCH | RW | 0x00000000 | Scratch register. | | + | | RO | Read-only |
- | | 0x0C | DATA_WIDTH | R | 0x00000008 | Data width of the SDI/SDO parallel interface. Is equal with the maximum supported transfer length in bits.| | + | | RW | Read-write |
- | | 0x40 | ENABLE | RW| 0x00000000 | Enable | + | | WO | Write-only | Writes will change |
- | | 0x80 | IRQ_MASK | + | | RW1C | Write-1-to-clear |
- | | [0] | CMD_ALMOST_EMPTY | RW | 0 | If set to 0 the CMD_ALMOST_EMPTY interrupt is masked. | | + | |
- | | [1] | SDO_ALMOST_EMPTY | RW | 0 | If set to 0 the SDO_ALMOST_EMPTY interrupt is masked. | | + | |
- | | [2] | SDI_ALMOST_FULL | RW | 0 | If set to 0 the SDI_ALMOST_FULL interrupt is masked. | | + | |
- | | [3] | SYNC_EVENT | RW | 0 | If set to 0 the SYNC_EVENT interrupt is masked. | | + | |
- | | 0x84 | IRQ_PENDING | W1C |0x00000000 | Pending IRQs with mask | | + | |
- | | 0x88 | IRQ_SOURCE | W1C |0x00000000 | Pending IRQs without mask | | + | |
- | | 0xc0 | SYNC_ID | R | 0x00000000 | Last synchronization event ID received from the SPI engine control interface. | | + | |
- | | 0xd0 | CMD_FIFO_ROOM | R | 0x???????? ((The reset value of the CMD_FIFO_ROOM register depends on the setting of the CMD_FIFO_ADDRESS_WIDTH parameter)) | Number of free entries in the command FIFO. | | + | |
- | | 0xd4 | SDO_FIFO_ROOM | R | 0x???????? ((The reset value of the SDO_FIFO_ROOM register depends on the setting of the SDO_FIFO_ADDRESS_WIDTH parameter)) | Number of free entries in the serial-data-out FIFO. | | + | |
- | | 0xd8 | SDI_FIFO_LEVEL | R | 0x00000000 | Number of valid entries in the serial-data-in FIFO. | | + | |
- | | 0xe0 | CMD_FIFO | W | 0x????????? | Command FIFO register. | + | |
- | | 0xe4 | SDO_FIFO | W | 0x????????? | SDO FIFO register. Writing | + | |
- | | 0xe8 | SDI_FIFO | R | 0x????????? | SDI FIFO register. Reading from this register removes | + | |
- | | 0xf0 | SDI_FIFO_PEEK | R| 0x???????? | SDI FIFO peek register. Reading from this register returns | + | |
- | | 0x100 | OFFLOAD0_EN | RW | 0 | Set this bit to enable the offload module. | | + | |
- | | 0x108 | OFFLOAD0_MEM_RESET | RW | 0 | Reset the memory | + | |
- | | 0x110 | OFFLOAD0_CDM_FIFO | W | 0x???????? | Offload command FIFO register. Writing | + | |
- | | 0x114 | OFFLOAD0_SDO_FIFO | W | 0x???????? | Offload SDO FIFO register. Writing to this register inserts an entry into the offload SDO FIFO. Writing to this register when the SDO FIFO is full has no effect and the written entry is discarded. Reading from this register always returns 0x00000000. | | + | |
===== Theory of Operation ===== | ===== Theory of Operation ===== | ||
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It is recommended that synchronization IDs are generated in a monotonic incrementing or decrementing manner. This makes it possible to easily check if an event has completed by checking if it is less or equal (incrementing IDs) or more or equal (decrementing IDs) to the ID of the last completed event. | It is recommended that synchronization IDs are generated in a monotonic incrementing or decrementing manner. This makes it possible to easily check if an event has completed by checking if it is less or equal (incrementing IDs) or more or equal (decrementing IDs) to the ID of the last completed event. | ||
+ | |||
==== Interrupts ==== | ==== Interrupts ==== | ||