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resources:fpga:peripherals:jesd204:tutorial:hdl_xilinx [12 Jun 2018 19:57] – [References] Lars-Peter Clausen | resources:fpga:peripherals:jesd204:tutorial:hdl_xilinx [14 Jan 2021 05:38] (current) – use wiki interwiki links Robin Getz | ||
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====== DAQ2 HDL Project for Xilinx ====== | ====== DAQ2 HDL Project for Xilinx ====== | ||
- | ===== Xilinx Block Diagram ===== | + | The reference design is a processor based embedded system. The sources are split into three different folders: |
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- | {{: | + | |
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- | The reference design is a processor based embedded system. The sources are split into three different folders: | + | |
* base design for the carrier board, [[https:// | * base design for the carrier board, [[https:// | ||
* base design for the evaluation board, [[https:// | * base design for the evaluation board, [[https:// | ||
* specific design for the project, in our case the ZCU102 [[https:// | * specific design for the project, in our case the ZCU102 [[https:// | ||
- | The reference design is a processor based (ARM or Microblaze) embedded system. A functional block diagram of the system is given above. The shared transceivers are followed by the individual JESD204B and ADC/DAC IP cores. The cores are programmable through an AXI-lite interface. | + | |
+ | ==== AD-FMCDAQ2-EBZ block diagram ==== | ||
+ | {{resources: | ||
+ | |||
+ | ==== Xilinx block diagram ==== | ||
+ | {{resources: | ||
+ | |||
+ | The reference design is a processor based (ARM or Microblaze) embedded system. A functional block diagram of the system is given above. The shared transceivers are followed by the individual JESD204B and ADC/DAC IP cores. The cores are programmable through an AXI-lite interface. | ||
The digital interface consists of 4 transmit and 4 receive lanes running at 10Gbps, by default. The transceivers interface the ADC/DAC cores at 128bits@250MHz. The data is sent or received based on the configuration of separate transmit and receive chains. | The digital interface consists of 4 transmit and 4 receive lanes running at 10Gbps, by default. The transceivers interface the ADC/DAC cores at 128bits@250MHz. The data is sent or received based on the configuration of separate transmit and receive chains. | ||
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===== Building the HDL Project ===== | ===== Building the HDL Project ===== | ||
- | When building the project, you should always use the recommended version of the tools for the specific [[https:// | + | When building the project, you should always use the recommended version of the tools for the specific [[/ |
< | < |